mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
160 lines
4.3 KiB
LLVM
160 lines
4.3 KiB
LLVM
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64
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; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32
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@c = common global i8 0, align 4
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@s = common global i16 0, align 4
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@i = common global i32 0, align 4
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@l = common global i64 0, align 8
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@uc = common global i8 0, align 4
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@us = common global i16 0, align 4
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@ui = common global i32 0, align 4
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@l1 = common global i64 0, align 8
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define i64 @func1() nounwind readonly {
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entry:
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; CHECK-N64: func1
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c)
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; CHECK-N64: lb ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: func1
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c)
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; CHECK-N32: lb ${{[0-9]+}}, 0($[[R0]])
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%0 = load i8, i8* @c, align 4
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%conv = sext i8 %0 to i64
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ret i64 %conv
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}
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define i64 @func2() nounwind readonly {
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entry:
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; CHECK-N64: func2
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s)
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; CHECK-N64: lh ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: func2
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s)
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; CHECK-N32: lh ${{[0-9]+}}, 0($[[R0]])
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%0 = load i16, i16* @s, align 4
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%conv = sext i16 %0 to i64
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ret i64 %conv
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}
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define i64 @func3() nounwind readonly {
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entry:
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; CHECK-N64: func3
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i)
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; CHECK-N64: lw ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: func3
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i)
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; CHECK-N32: lw ${{[0-9]+}}, 0($[[R0]])
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%0 = load i32, i32* @i, align 4
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%conv = sext i32 %0 to i64
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ret i64 %conv
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}
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define i64 @func4() nounwind readonly {
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entry:
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; CHECK-N64: func4
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l)
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; CHECK-N64: ld ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: func4
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l)
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; CHECK-N32: ld ${{[0-9]+}}, 0($[[R0]])
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%0 = load i64, i64* @l, align 8
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ret i64 %0
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}
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define i64 @ufunc1() nounwind readonly {
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entry:
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; CHECK-N64: ufunc1
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(uc)
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; CHECK-N64: lbu ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: ufunc1
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(uc)
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; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]])
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%0 = load i8, i8* @uc, align 4
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%conv = zext i8 %0 to i64
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ret i64 %conv
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}
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define i64 @ufunc2() nounwind readonly {
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entry:
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; CHECK-N64: ufunc2
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(us)
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; CHECK-N64: lhu ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: ufunc2
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(us)
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; CHECK-N32: lhu ${{[0-9]+}}, 0($[[R0]])
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%0 = load i16, i16* @us, align 4
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%conv = zext i16 %0 to i64
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ret i64 %conv
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}
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define i64 @ufunc3() nounwind readonly {
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entry:
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; CHECK-N64: ufunc3
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(ui)
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; CHECK-N64: lwu ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: ufunc3
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(ui)
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; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]])
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%0 = load i32, i32* @ui, align 4
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%conv = zext i32 %0 to i64
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ret i64 %conv
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}
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define void @sfunc1() nounwind {
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entry:
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; CHECK-N64: sfunc1
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c)
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; CHECK-N64: sb ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: sfunc1
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c)
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; CHECK-N32: sb ${{[0-9]+}}, 0($[[R0]])
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%0 = load i64, i64* @l1, align 8
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%conv = trunc i64 %0 to i8
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store i8 %conv, i8* @c, align 4
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ret void
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}
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define void @sfunc2() nounwind {
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entry:
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; CHECK-N64: sfunc2
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s)
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; CHECK-N64: sh ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: sfunc2
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s)
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; CHECK-N32: sh ${{[0-9]+}}, 0($[[R0]])
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%0 = load i64, i64* @l1, align 8
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%conv = trunc i64 %0 to i16
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store i16 %conv, i16* @s, align 4
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ret void
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}
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define void @sfunc3() nounwind {
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entry:
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; CHECK-N64: sfunc3
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i)
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; CHECK-N64: sw ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: sfunc3
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i)
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; CHECK-N32: sw ${{[0-9]+}}, 0($[[R0]])
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%0 = load i64, i64* @l1, align 8
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%conv = trunc i64 %0 to i32
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store i32 %conv, i32* @i, align 4
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ret void
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}
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define void @sfunc4() nounwind {
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entry:
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; CHECK-N64: sfunc4
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l)
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; CHECK-N64: sd ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: sfunc4
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l)
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; CHECK-N32: sd ${{[0-9]+}}, 0($[[R0]])
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%0 = load i64, i64* @l1, align 8
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store i64 %0, i64* @l, align 8
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ret void
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}
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