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https://github.com/c64scene-ar/llvm-6502.git
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95355e6498
Summary: We used to assume V->RAUW only modifies the operand list of V's user. However, if V and V's user are Constants, RAUW may replace and invalidate V's user entirely. This patch fixes the above issue by letting the caller replace the operand instead of calling RAUW on Constants. Test Plan: @nested_const_expr and @rauw in access-non-generic.ll Reviewers: broune, jholewinski Reviewed By: broune, jholewinski Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10345 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239435 91177308-0d34-0410-b5e6-96231b3b80d8
130 lines
5.0 KiB
LLVM
130 lines
5.0 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix PTX
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix PTX
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; RUN: opt < %s -S -nvptx-favor-non-generic -dce | FileCheck %s --check-prefix IR
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@array = internal addrspace(3) global [10 x float] zeroinitializer, align 4
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@scalar = internal addrspace(3) global float 0.000000e+00, align 4
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; Verifies nvptx-favor-non-generic correctly optimizes generic address space
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; usage to non-generic address space usage for the patterns we claim to handle:
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; 1. load cast
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; 2. store cast
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; 3. load gep cast
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; 4. store gep cast
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; gep and cast can be an instruction or a constant expression. This function
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; tries all possible combinations.
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define float @ld_st_shared_f32(i32 %i, float %v) {
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; IR-LABEL: @ld_st_shared_f32
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; IR-NOT: addrspacecast
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; PTX-LABEL: ld_st_shared_f32(
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; load cast
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%1 = load float, float* addrspacecast (float addrspace(3)* @scalar to float*), align 4
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; PTX: ld.shared.f32 %f{{[0-9]+}}, [scalar];
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; store cast
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store float %v, float* addrspacecast (float addrspace(3)* @scalar to float*), align 4
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; PTX: st.shared.f32 [scalar], %f{{[0-9]+}};
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; use syncthreads to disable optimizations across components
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call void @llvm.cuda.syncthreads()
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; PTX: bar.sync 0;
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; cast; load
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%2 = addrspacecast float addrspace(3)* @scalar to float*
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%3 = load float, float* %2, align 4
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; PTX: ld.shared.f32 %f{{[0-9]+}}, [scalar];
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; cast; store
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store float %v, float* %2, align 4
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; PTX: st.shared.f32 [scalar], %f{{[0-9]+}};
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call void @llvm.cuda.syncthreads()
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; PTX: bar.sync 0;
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; load gep cast
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%4 = load float, float* getelementptr inbounds ([10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5), align 4
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; PTX: ld.shared.f32 %f{{[0-9]+}}, [array+20];
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; store gep cast
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store float %v, float* getelementptr inbounds ([10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5), align 4
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; PTX: st.shared.f32 [array+20], %f{{[0-9]+}};
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call void @llvm.cuda.syncthreads()
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; PTX: bar.sync 0;
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; gep cast; load
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%5 = getelementptr inbounds [10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5
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%6 = load float, float* %5, align 4
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; PTX: ld.shared.f32 %f{{[0-9]+}}, [array+20];
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; gep cast; store
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store float %v, float* %5, align 4
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; PTX: st.shared.f32 [array+20], %f{{[0-9]+}};
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call void @llvm.cuda.syncthreads()
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; PTX: bar.sync 0;
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; cast; gep; load
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%7 = addrspacecast [10 x float] addrspace(3)* @array to [10 x float]*
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%8 = getelementptr inbounds [10 x float], [10 x float]* %7, i32 0, i32 %i
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%9 = load float, float* %8, align 4
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; PTX: ld.shared.f32 %f{{[0-9]+}}, [%{{(r|rl|rd)[0-9]+}}];
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; cast; gep; store
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store float %v, float* %8, align 4
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; PTX: st.shared.f32 [%{{(r|rl|rd)[0-9]+}}], %f{{[0-9]+}};
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call void @llvm.cuda.syncthreads()
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; PTX: bar.sync 0;
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%sum2 = fadd float %1, %3
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%sum3 = fadd float %sum2, %4
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%sum4 = fadd float %sum3, %6
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%sum5 = fadd float %sum4, %9
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ret float %sum5
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}
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; When hoisting an addrspacecast between different pointer types, replace the
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; addrspacecast with a bitcast.
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define i32 @ld_int_from_float() {
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; IR-LABEL: @ld_int_from_float
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; IR: load i32, i32 addrspace(3)* bitcast (float addrspace(3)* @scalar to i32 addrspace(3)*)
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; PTX-LABEL: ld_int_from_float(
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; PTX: ld.shared.u{{(32|64)}}
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%1 = load i32, i32* addrspacecast(float addrspace(3)* @scalar to i32*), align 4
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ret i32 %1
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}
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define i32 @ld_int_from_global_float(float addrspace(1)* %input, i32 %i, i32 %j) {
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; IR-LABEL: @ld_int_from_global_float(
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; PTX-LABEL: ld_int_from_global_float(
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%1 = addrspacecast float addrspace(1)* %input to float*
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%2 = getelementptr float, float* %1, i32 %i
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; IR-NEXT: getelementptr float, float addrspace(1)* %input, i32 %i
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%3 = getelementptr float, float* %2, i32 %j
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; IR-NEXT: getelementptr float, float addrspace(1)* {{%[^,]+}}, i32 %j
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%4 = bitcast float* %3 to i32*
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; IR-NEXT: bitcast float addrspace(1)* {{%[^ ]+}} to i32 addrspace(1)*
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%5 = load i32, i32* %4
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; IR-NEXT: load i32, i32 addrspace(1)* {{%.+}}
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; PTX-LABEL: ld.global
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ret i32 %5
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}
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define void @nested_const_expr() {
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; PTX-LABEL: nested_const_expr(
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; store 1 to bitcast(gep(addrspacecast(array), 0, 1))
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store i32 1, i32* bitcast (float* getelementptr ([10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i64 0, i64 1) to i32*), align 4
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; PTX: mov.u32 %r1, 1;
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; PTX-NEXT: st.shared.u32 [array+4], %r1;
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ret void
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}
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define void @rauw(float addrspace(1)* %input) {
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%generic_input = addrspacecast float addrspace(1)* %input to float*
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%addr = getelementptr float, float* %generic_input, i64 10
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%v = load float, float* %addr
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store float %v, float* %addr
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ret void
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; IR-LABEL: @rauw(
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; IR-NEXT: %1 = getelementptr float, float addrspace(1)* %input, i64 10
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; IR-NEXT: %v = load float, float addrspace(1)* %1
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; IR-NEXT: store float %v, float addrspace(1)* %1
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; IR-NEXT: ret void
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}
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declare void @llvm.cuda.syncthreads() #3
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attributes #3 = { noduplicate nounwind }
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