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d64b5c82b9
the stored register is killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
227 lines
8.7 KiB
C++
227 lines
8.7 KiB
C++
//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86REGISTERINFO_H
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#define X86REGISTERINFO_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "X86GenRegisterInfo.h.inc"
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namespace llvm {
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class Type;
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class TargetInstrInfo;
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class X86TargetMachine;
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/// N86 namespace - Native X86 register numbers
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///
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namespace N86 {
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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/// DWARFFlavour - Flavour of dwarf regnumbers
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///
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namespace DWARFFlavour {
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enum {
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X86_64 = 0, X86_32_Darwin = 1, X86_32_ELF = 2
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};
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}
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class X86RegisterInfo : public X86GenRegisterInfo {
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public:
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X86TargetMachine &TM;
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const TargetInstrInfo &TII;
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private:
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/// Is64Bit - Is the target 64-bits.
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///
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bool Is64Bit;
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/// SlotSize - Stack slot size in bytes.
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///
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unsigned SlotSize;
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/// StackAlign - Default stack alignment.
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///
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unsigned StackAlign;
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/// StackPtr - X86 physical register used as stack ptr.
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///
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unsigned StackPtr;
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/// FramePtr - X86 physical register used as frame ptr.
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///
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unsigned FramePtr;
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/// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
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/// RegOp2MemOpTable2 - Load / store folding opcode maps.
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///
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DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr;
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DenseMap<unsigned*, unsigned> RegOp2MemOpTable0;
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DenseMap<unsigned*, unsigned> RegOp2MemOpTable1;
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DenseMap<unsigned*, unsigned> RegOp2MemOpTable2;
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/// MemOp2RegOpTable - Load / store unfolding opcode map.
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///
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DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
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public:
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X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
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/// getX86RegNum - Returns the native X86 register number for the given LLVM
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/// register identifier.
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unsigned getX86RegNum(unsigned RegNo);
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/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
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/// (created by TableGen) for target dependencies.
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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/// Code Generation virtual methods...
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///
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const;
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const;
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void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, const MachineInstr *Orig) const;
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/// foldMemoryOperand - If this target supports it, fold a load or store of
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/// the specified stack slot into the specified machine instruction for the
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/// specified operand(s). If this is possible, the target should perform the
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/// folding and return true, otherwise it should return false. If it folds
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/// the instruction, it is likely that the MachineInstruction the iterator
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/// references has been changed.
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MachineInstr* foldMemoryOperand(MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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MachineInstr* foldMemoryOperand(MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const;
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/// canFoldMemoryOperand - Returns true if the specified load / store is
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/// folding is possible.
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bool canFoldMemoryOperand(MachineInstr*, SmallVectorImpl<unsigned> &) const;
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/// unfoldMemoryOperand - Separate a single instruction which folded a load or
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/// a store or a load and a store into two or more instruction. If this is
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/// possible, returns true as well as the new instructions by reference.
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bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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SmallVectorImpl<SDNode*> &NewNodes) const;
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/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
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/// instruction after load / store are unfolded from an instruction of the
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/// specified opcode. It returns zero if the specified unfolding is not
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/// possible.
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unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
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bool UnfoldLoad, bool UnfoldStore) const;
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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/// callee-save registers on this target.
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const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
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/// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
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/// register classes to spill each callee-saved register with. The order and
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/// length of this list match the getCalleeSavedRegs() list.
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses and
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/// should be considered unavailable at all times, e.g. SP, RA. This is used by
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/// register scavenger to determine what registers are free.
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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bool hasReservedCallFrame(MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, RegScavenger *RS = NULL) const;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(MachineFunction &MF) const;
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void getInitialFrameState(std::vector<MachineMove> &Moves) const;
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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private:
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MachineInstr* foldMemoryOperand(MachineInstr* MI,
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unsigned OpNum,
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SmallVector<MachineOperand,4> &MOs) const;
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};
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// getX86SubSuperRegister - X86 utility function. It returns the sub or super
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// register of a specific X86 register.
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// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
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unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false);
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} // End llvm namespace
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#endif
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