mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
133 lines
4.3 KiB
LLVM
133 lines
4.3 KiB
LLVM
; RUN: llc < %s -mtriple armv8 -mattr=+neon | FileCheck %s
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; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST
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define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
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; CHECK-LABEL: vmaxnmq:
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; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x float> %tmp3
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}
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define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind {
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; CHECK-LABEL: vmaxnmd:
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; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x float> %tmp3
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}
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define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
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; CHECK-LABEL: vminnmq:
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; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x float> %tmp3
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}
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define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind {
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; CHECK-LABEL: vminnmd:
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; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x float> %tmp3
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}
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define float @fp-armv8_vminnm_o(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_o":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vminnm.f32
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; CHECK-LABEL: "fp-armv8_vminnm_o":
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; CHECK-NOT: vminnm.f32
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%cmp = fcmp olt float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vminnm_o_rev(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_o_rev":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vminnm.f32
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; CHECK-LABEL: "fp-armv8_vminnm_o_rev":
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; CHECK-NOT: vminnm.f32
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%cmp = fcmp ogt float %a, %b
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%cond = select i1 %cmp, float %b, float %a
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ret float %cond
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}
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define float @fp-armv8_vminnm_u(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_u":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vminnm.f32
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; CHECK-LABEL: "fp-armv8_vminnm_u":
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; CHECK-NOT: vminnm.f32
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%cmp = fcmp ult float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vminnm_u_rev(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_u_rev":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vminnm.f32
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; CHECK-LABEL: "fp-armv8_vminnm_u_rev":
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; CHECK-NOT: vminnm.f32
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%cmp = fcmp ugt float %a, %b
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%cond = select i1 %cmp, float %b, float %a
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_o(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_o":
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; CHECK-NOT: vmaxnm.f32
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%cmp = fcmp ogt float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o_rev":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_o_rev":
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; CHECK-NOT: vmaxnm.f32
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%cmp = fcmp olt float %a, %b
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%cond = select i1 %cmp, float %b, float %a
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_u(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_u":
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; CHECK-NOT: vmaxnm.f32
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%cmp = fcmp ugt float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u_rev":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_u_rev":
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; CHECK-NOT: vmaxnm.f32
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%cmp = fcmp ult float %a, %b
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%cond = select i1 %cmp, float %b, float %a
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ret float %cond
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}
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declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
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