mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
236 lines
9.3 KiB
LLVM
236 lines
9.3 KiB
LLVM
; RUN: llc < %s -mcpu=x86-64 -mattr=-sse2 | FileCheck %s --check-prefix=SSE1
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target triple = "x86_64-unknown-unknown"
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define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_0001:
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; SSE1: # BB#0:
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_0020:
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; SSE1: # BB#0:
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_0300:
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; SSE1: # BB#0:
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3,0,0]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_1000:
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; SSE1: # BB#0:
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0,0,0]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_2200:
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; SSE1: # BB#0:
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,2,0,0]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_3330:
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; SSE1: # BB#0:
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,0]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_3210:
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; SSE1: # BB#0:
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_0011(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_0011:
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; SSE1: # BB#0:
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; SSE1-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0,0,1,1]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_2233(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_2233:
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; SSE1: # BB#0:
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; SSE1-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2,2,3,3]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_0022(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_0022:
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; SSE1: # BB#0:
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,2]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_1133(<4 x float> %a, <4 x float> %b) {
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; SSE1-LABEL: shuffle_v4f32_1133:
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; SSE1: # BB#0:
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_4zzz(<4 x float> %a) {
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; SSE1-LABEL: shuffle_v4f32_4zzz:
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; SSE1: # BB#0:
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; SSE1-NEXT: xorps %xmm1, %xmm1
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; SSE1-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSE1-NEXT: movaps %xmm1, %xmm0
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_z4zz(<4 x float> %a) {
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; SSE1-LABEL: shuffle_v4f32_z4zz:
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; SSE1: # BB#0:
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; SSE1-NEXT: xorps %xmm1, %xmm1
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 4, i32 3, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) {
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; SSE1-LABEL: shuffle_v4f32_zz4z:
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; SSE1: # BB#0:
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; SSE1-NEXT: xorps %xmm1, %xmm1
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
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; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
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; SSE1-NEXT: movaps %xmm1, %xmm0
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 0, i32 4, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_zuu4(<4 x float> %a) {
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; SSE1-LABEL: shuffle_v4f32_zuu4:
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; SSE1: # BB#0:
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; SSE1-NEXT: xorps %xmm1, %xmm1
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; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
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; SSE1-NEXT: movaps %xmm1, %xmm0
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 4>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_zzz7(<4 x float> %a) {
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; SSE1-LABEL: shuffle_v4f32_zzz7:
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; SSE1: # BB#0:
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; SSE1-NEXT: xorps %xmm1, %xmm1
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
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; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
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; SSE1-NEXT: movaps %xmm1, %xmm0
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) {
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; SSE1-LABEL: shuffle_v4f32_z6zz:
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; SSE1: # BB#0:
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; SSE1-NEXT: xorps %xmm1, %xmm1
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0]
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
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; SSE1-NEXT: retq
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%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
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ret <4 x float> %shuffle
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}
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define <4 x float> @insert_reg_and_zero_v4f32(float %a) {
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; SSE1-LABEL: insert_reg_and_zero_v4f32:
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; SSE1: # BB#0:
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; SSE1-NEXT: xorps %xmm1, %xmm1
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; SSE1-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSE1-NEXT: movaps %xmm1, %xmm0
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; SSE1-NEXT: retq
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%v = insertelement <4 x float> undef, float %a, i32 0
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%shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %shuffle
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}
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define <4 x float> @insert_mem_and_zero_v4f32(float* %ptr) {
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; SSE1-LABEL: insert_mem_and_zero_v4f32:
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; SSE1: # BB#0:
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; SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE1-NEXT: retq
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%a = load float, float* %ptr
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%v = insertelement <4 x float> undef, float %a, i32 0
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%shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %shuffle
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}
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define <4 x float> @insert_mem_lo_v4f32(<2 x float>* %ptr, <4 x float> %b) {
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; SSE1-LABEL: insert_mem_lo_v4f32:
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; SSE1: # BB#0:
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; SSE1-NEXT: movq (%rdi), %rax
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; SSE1-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; SSE1-NEXT: shrq $32, %rax
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; SSE1-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; SSE1-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSE1-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; SSE1-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
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; SSE1-NEXT: xorps %xmm2, %xmm2
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; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3]
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; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
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; SSE1-NEXT: movaps %xmm1, %xmm0
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; SSE1-NEXT: retq
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%a = load <2 x float>, <2 x float>* %ptr
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%v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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ret <4 x float> %shuffle
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}
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define <4 x float> @insert_mem_hi_v4f32(<2 x float>* %ptr, <4 x float> %b) {
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; SSE1-LABEL: insert_mem_hi_v4f32:
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; SSE1: # BB#0:
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; SSE1-NEXT: movq (%rdi), %rax
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; SSE1-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; SSE1-NEXT: shrq $32, %rax
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; SSE1-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; SSE1-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSE1-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; SSE1-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
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; SSE1-NEXT: xorps %xmm2, %xmm2
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; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3]
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,1]
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; SSE1-NEXT: retq
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%a = load <2 x float>, <2 x float>* %ptr
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%v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_mem_v4f32_3210(<4 x float>* %ptr) {
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; SSE1-LABEL: shuffle_mem_v4f32_3210:
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; SSE1: # BB#0:
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; SSE1-NEXT: movaps (%rdi), %xmm0
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; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
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; SSE1-NEXT: retq
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%a = load <4 x float>, <4 x float>* %ptr
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%shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x float> %shuffle
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}
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