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https://github.com/c64scene-ar/llvm-6502.git
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9a06cce0f2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25900 91177308-0d34-0410-b5e6-96231b3b80d8
270 lines
11 KiB
C++
270 lines
11 KiB
C++
//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the TargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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TargetLowering::TargetLowering(TargetMachine &tm)
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: TM(tm), TD(TM.getTargetData()) {
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assert(ISD::BUILTIN_OP_END <= 128 &&
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"Fixed size array in TargetLowering is not large enough!");
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// All operations default to being supported.
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memset(OpActions, 0, sizeof(OpActions));
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IsLittleEndian = TD.isLittleEndian();
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ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
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ShiftAmtHandling = Undefined;
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memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
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maxStoresPerMemSet = maxStoresPerMemCpy = maxStoresPerMemMove = 8;
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allowUnalignedMemoryAccesses = false;
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UseUnderscoreSetJmpLongJmp = false;
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IntDivIsCheap = false;
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Pow2DivIsCheap = false;
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StackPointerRegisterToSaveRestore = 0;
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SchedPreferenceInfo = SchedulingForLatency;
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}
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TargetLowering::~TargetLowering() {}
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/// setValueTypeAction - Set the action for a particular value type. This
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/// assumes an action has not already been set for this value type.
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static void SetValueTypeAction(MVT::ValueType VT,
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TargetLowering::LegalizeAction Action,
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TargetLowering &TLI,
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MVT::ValueType *TransformToType,
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TargetLowering::ValueTypeActionImpl &ValueTypeActions) {
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ValueTypeActions.setTypeAction(VT, Action);
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if (Action == TargetLowering::Promote) {
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MVT::ValueType PromoteTo;
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if (VT == MVT::f32)
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PromoteTo = MVT::f64;
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else {
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unsigned LargerReg = VT+1;
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while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) {
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++LargerReg;
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assert(MVT::isInteger((MVT::ValueType)LargerReg) &&
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"Nothing to promote to??");
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}
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PromoteTo = (MVT::ValueType)LargerReg;
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}
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assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) &&
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MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) &&
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"Can only promote from int->int or fp->fp!");
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assert(VT < PromoteTo && "Must promote to a larger type!");
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TransformToType[VT] = PromoteTo;
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} else if (Action == TargetLowering::Expand) {
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assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
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"Cannot expand this type: target must support SOME integer reg!");
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// Expand to the next smaller integer type!
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TransformToType[VT] = (MVT::ValueType)(VT-1);
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}
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}
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/// computeRegisterProperties - Once all of the register classes are added,
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/// this allows us to compute derived properties we expose.
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void TargetLowering::computeRegisterProperties() {
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assert(MVT::LAST_VALUETYPE <= 32 &&
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"Too many value types for ValueTypeActions to hold!");
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// Everything defaults to one.
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for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
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NumElementsForVT[i] = 1;
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// Find the largest integer register class.
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unsigned LargestIntReg = MVT::i128;
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for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
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assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
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// Every integer value type larger than this largest register takes twice as
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// many registers to represent as the previous ValueType.
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unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
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for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
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NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
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// Inspect all of the ValueType's possible, deciding how to process them.
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for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
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// If we are expanding this type, expand it!
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if (getNumElements((MVT::ValueType)IntReg) != 1)
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SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
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ValueTypeActions);
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else if (!isTypeLegal((MVT::ValueType)IntReg))
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// Otherwise, if we don't have native support, we must promote to a
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// larger type.
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SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this,
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TransformToType, ValueTypeActions);
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else
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TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
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// If the target does not have native support for F32, promote it to F64.
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if (!isTypeLegal(MVT::f32))
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SetValueTypeAction(MVT::f32, Promote, *this,
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TransformToType, ValueTypeActions);
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else
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TransformToType[MVT::f32] = MVT::f32;
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// Set MVT::Vector to always be Expanded
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SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
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ValueTypeActions);
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assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
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TransformToType[MVT::f64] = MVT::f64;
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}
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const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
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return NULL;
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}
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/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
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/// this predicate to simplify operations downstream. Op and Mask are known to
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/// be the same type.
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bool TargetLowering::MaskedValueIsZero(const SDOperand &Op,
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uint64_t Mask) const {
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unsigned SrcBits;
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if (Mask == 0) return true;
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// If we know the result of a setcc has the top bits zero, use this info.
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switch (Op.getOpcode()) {
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case ISD::Constant:
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return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
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case ISD::SETCC:
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return ((Mask & 1) == 0) &&
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getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
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case ISD::ZEXTLOAD:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::ZERO_EXTEND:
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SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
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return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)));
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case ISD::ANY_EXTEND:
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// If the mask only includes bits in the low part, recurse.
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SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
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if (Mask >> SrcBits) return false; // Use of unknown top bits.
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return MaskedValueIsZero(Op.getOperand(0), Mask);
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case ISD::AssertZext:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::AND:
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// If either of the operands has zero bits, the result will too.
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if (MaskedValueIsZero(Op.getOperand(1), Mask) ||
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MaskedValueIsZero(Op.getOperand(0), Mask))
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return true;
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// (X & C1) & C2 == 0 iff C1 & C2 == 0.
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask);
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return false;
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case ISD::OR:
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case ISD::XOR:
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return MaskedValueIsZero(Op.getOperand(0), Mask) &&
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MaskedValueIsZero(Op.getOperand(1), Mask);
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case ISD::SELECT:
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return MaskedValueIsZero(Op.getOperand(1), Mask) &&
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MaskedValueIsZero(Op.getOperand(2), Mask);
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case ISD::SELECT_CC:
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return MaskedValueIsZero(Op.getOperand(2), Mask) &&
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MaskedValueIsZero(Op.getOperand(3), Mask);
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case ISD::SRL:
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// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask << ShAmt->getValue();
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SrcBits = MVT::getSizeInBits(Op.getValueType());
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if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
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return MaskedValueIsZero(Op.getOperand(0), NewVal);
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}
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return false;
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case ISD::SHL:
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// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask >> ShAmt->getValue();
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return MaskedValueIsZero(Op.getOperand(0), NewVal);
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}
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return false;
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case ISD::ADD:
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// (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
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if ((Mask&(Mask+1)) == 0) { // All low bits
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if (MaskedValueIsZero(Op.getOperand(0), Mask) &&
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MaskedValueIsZero(Op.getOperand(1), Mask))
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return true;
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}
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break;
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case ISD::SUB:
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if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
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// We know that the top bits of C-X are clear if X contains less bits
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// than C (i.e. no wrap-around can happen). For example, 20-X is
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// positive if we can prove that X is >= 0 and < 16.
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unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
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if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
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unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
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uint64_t MaskV = (1ULL << (63-NLZ))-1;
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if (MaskedValueIsZero(Op.getOperand(1), ~MaskV)) {
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// High bits are clear this value is known to be >= C.
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unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
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if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
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return true;
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}
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}
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}
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break;
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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// Bit counting instructions can not set the high bits of the result
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// register. The max number of bits sets depends on the input.
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return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
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default:
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// Allow the target to implement this method for its nodes.
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if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
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return isMaskedValueZeroForTargetNode(Op, Mask);
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break;
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}
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return false;
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}
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bool TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
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uint64_t Mask) const {
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assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
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"Should use MaskedValueIsZero if you don't know whether Op"
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" is a target node!");
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return false;
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}
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std::vector<unsigned> TargetLowering::
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getRegForInlineAsmConstraint(const std::string &Constraint) const {
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// Not a physreg, must not be a register reference or something.
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if (Constraint[0] != '{') return std::vector<unsigned>();
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assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
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// Remove the braces from around the name.
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std::string RegName(Constraint.begin()+1, Constraint.end()-1);
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// Scan to see if this constraint is a register name.
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const MRegisterInfo *RI = TM.getRegisterInfo();
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for (unsigned i = 1, e = RI->getNumRegs(); i != e; ++i) {
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if (const char *Name = RI->get(i).Name)
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if (StringsEqualNoCase(RegName, Name))
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return std::vector<unsigned>(1, i);
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}
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// Unknown physreg.
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return std::vector<unsigned>();
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}
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