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Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16639 91177308-0d34-0410-b5e6-96231b3b80d8
457 lines
16 KiB
C++
457 lines
16 KiB
C++
//===-- X86AsmPrinter.cpp - Convert X86 LLVM code to Intel assembly -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to Intel-format assembly language. This
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// printer is the output mechanism used by `llc' and `lli -print-machineinstrs'
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// on X86.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86TargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Module.h"
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#include "llvm/Assembly/Writer.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Mangler.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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namespace {
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Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
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enum AsmWriterFlavor { att, intel };
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cl::opt<AsmWriterFlavor>
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AsmWriterFlavor("x86-asm-syntax",
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cl::desc("Choose style of code to emit from X86 backend:"),
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cl::values(
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clEnumVal(att, " Emit AT&T Style"),
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clEnumVal(intel, " Emit Intel Style"),
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clEnumValEnd),
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cl::init(intel));
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struct GasBugWorkaroundEmitter : public MachineCodeEmitter {
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GasBugWorkaroundEmitter(std::ostream& o)
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: O(o), OldFlags(O.flags()), firstByte(true) {
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O << std::hex;
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}
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~GasBugWorkaroundEmitter() {
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O.flags(OldFlags);
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}
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virtual void emitByte(unsigned char B) {
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if (!firstByte) O << "\n\t";
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firstByte = false;
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O << ".byte 0x" << (unsigned) B;
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}
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// These should never be called
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virtual void emitWord(unsigned W) { assert(0); }
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virtual uint64_t getGlobalValueAddress(GlobalValue *V) { abort(); }
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virtual uint64_t getGlobalValueAddress(const std::string &Name) { abort(); }
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virtual uint64_t getConstantPoolEntryAddress(unsigned Index) { abort(); }
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virtual uint64_t getCurrentPCValue() { abort(); }
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virtual uint64_t forceCompilationOf(Function *F) { abort(); }
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private:
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std::ostream& O;
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std::ios::fmtflags OldFlags;
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bool firstByte;
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};
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struct X86IntelAsmPrinter : public AsmPrinter {
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X86IntelAsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) { }
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virtual const char *getPassName() const {
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return "X86 Assembly Printer";
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}
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description. This method returns true if the
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/// machine instruction was sufficiently described to print it, otherwise it
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/// returns false.
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bool printInstruction(const MachineInstr *MI);
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// This method is used by the tablegen'erated instruction printer.
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void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
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const MachineOperand &MO = MI->getOperand(OpNo);
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if (MO.getType() == MachineOperand::MO_MachineRegister) {
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assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
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// Bug Workaround: See note in Printer::doInitialization about %.
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O << "%" << TM.getRegisterInfo()->get(MO.getReg()).Name;
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} else {
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printOp(MO);
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}
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}
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void printCallOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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printOp(MI->getOperand(OpNo), true); // Don't print "OFFSET".
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}
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void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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switch (VT) {
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default: assert(0 && "Unknown arg size!");
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case MVT::i8: O << "BYTE PTR "; break;
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case MVT::i16: O << "WORD PTR "; break;
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case MVT::i32:
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case MVT::f32: O << "DWORD PTR "; break;
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case MVT::i64:
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case MVT::f64: O << "QWORD PTR "; break;
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case MVT::f80: O << "XWORD PTR "; break;
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}
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printMemReference(MI, OpNo);
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}
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void printMachineInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
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void printMemReference(const MachineInstr *MI, unsigned Op);
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void printConstantPool(MachineConstantPool *MCP);
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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bool doFinalization(Module &M);
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};
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} // end of anonymous namespace
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/// createX86CodePrinterPass - Returns a pass that prints the X86
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/// assembly code for a MachineFunction to the given output stream,
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/// using the given target machine description. This should work
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/// regardless of whether the function is in SSA form.
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///
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FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
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if (AsmWriterFlavor != intel) {
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std::cerr << "AT&T syntax not fully implemented yet!\n";
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abort();
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}
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return new X86IntelAsmPrinter(o, tm);
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}
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// Include the auto-generated portion of the assembly writer.
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#include "X86GenIntelAsmWriter.inc"
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/// printConstantPool - Print to the current output stream assembly
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/// representations of the constants in the constant pool MCP. This is
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/// used to print out constants which have been "spilled to memory" by
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/// the code generator.
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///
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void X86IntelAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
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const std::vector<Constant*> &CP = MCP->getConstants();
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const TargetData &TD = TM.getTargetData();
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if (CP.empty()) return;
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for (unsigned i = 0, e = CP.size(); i != e; ++i) {
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O << "\t.section .rodata\n";
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emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType()));
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O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString
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<< *CP[i] << "\n";
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emitGlobalConstant(CP[i]);
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}
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}
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/// runOnMachineFunction - This uses the printMachineInstruction()
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/// method to print assembly for each instruction.
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///
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bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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setupMachineFunction(MF);
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O << "\n\n";
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// Print out constants referenced by the function
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printConstantPool(MF.getConstantPool());
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// Print out labels for the function.
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O << "\t.text\n";
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emitAlignment(4);
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O << "\t.globl\t" << CurrentFnName << "\n";
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O << "\t.type\t" << CurrentFnName << ", @function\n";
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O << CurrentFnName << ":\n";
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// Print out code for the function.
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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// Print a label for the basic block.
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O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
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<< CommentString << " " << I->getBasicBlock()->getName() << "\n";
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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// Print the assembly for the instruction.
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O << "\t";
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printMachineInstruction(II);
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}
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}
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// We didn't modify anything.
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return false;
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}
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static bool isScale(const MachineOperand &MO) {
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return MO.isImmediate() &&
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(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
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MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
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}
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static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFrameIndex()) return true;
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if (MI->getOperand(Op).isConstantPoolIndex()) return true;
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isRegister() && isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isRegister() && MI->getOperand(Op+3).isImmediate();
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}
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void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
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bool elideOffsetKeyword /* = false */) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (Value *V = MO.getVRegValueOrNull()) {
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O << "<" << V->getName() << ">";
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return;
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
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// Bug Workaround: See note in Printer::doInitialization about %.
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O << "%" << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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O << (int)MO.getImmedValue();
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return;
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case MachineOperand::MO_MachineBasicBlock: {
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MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
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O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
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<< "_" << MBBOp->getNumber () << "\t# "
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<< MBBOp->getBasicBlock ()->getName ();
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return;
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}
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case MachineOperand::MO_PCRelativeDisp:
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std::cerr << "Shouldn't use addPCDisp() when building X86 MachineInstrs";
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abort ();
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return;
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case MachineOperand::MO_GlobalAddress:
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if (!elideOffsetKeyword)
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O << "OFFSET ";
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O << Mang->getValueName(MO.getGlobal());
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return;
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case MachineOperand::MO_ExternalSymbol:
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O << MO.getSymbolName();
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return;
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default:
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O << "<unknown operand type>"; return;
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}
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}
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void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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if (MI->getOperand(Op).isFrameIndex()) {
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O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
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if (MI->getOperand(Op+3).getImmedValue())
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O << " + " << MI->getOperand(Op+3).getImmedValue();
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O << "]";
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return;
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} else if (MI->getOperand(Op).isConstantPoolIndex()) {
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O << "[.CPI" << CurrentFnName << "_"
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<< MI->getOperand(Op).getConstantPoolIndex();
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if (MI->getOperand(Op+3).getImmedValue())
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O << " + " << MI->getOperand(Op+3).getImmedValue();
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O << "]";
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return;
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}
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const MachineOperand &BaseReg = MI->getOperand(Op);
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int ScaleVal = MI->getOperand(Op+1).getImmedValue();
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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int DispVal = MI->getOperand(Op+3).getImmedValue();
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O << "[";
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bool NeedPlus = false;
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if (BaseReg.getReg()) {
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printOp(BaseReg);
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NeedPlus = true;
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}
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if (IndexReg.getReg()) {
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if (NeedPlus) O << " + ";
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if (ScaleVal != 1)
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O << ScaleVal << "*";
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printOp(IndexReg);
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NeedPlus = true;
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}
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if (DispVal) {
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if (NeedPlus)
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if (DispVal > 0)
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O << " + ";
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else {
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O << " - ";
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DispVal = -DispVal;
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}
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O << DispVal;
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}
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O << "]";
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}
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/// printMachineInstruction -- Print out a single X86 LLVM instruction
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/// MI in Intel syntax to the current output stream.
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///
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void X86IntelAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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++EmittedInsts;
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// gas bugs:
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//
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// The 80-bit FP store-pop instruction "fstp XWORD PTR [...]" is misassembled
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// by gas in intel_syntax mode as its 32-bit equivalent "fstp DWORD PTR
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// [...]". Workaround: Output the raw opcode bytes instead of the instruction.
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//
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// The 80-bit FP load instruction "fld XWORD PTR [...]" is misassembled by gas
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// in intel_syntax mode as its 32-bit equivalent "fld DWORD PTR
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// [...]". Workaround: Output the raw opcode bytes instead of the instruction.
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//
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// gas intel_syntax mode treats "fild QWORD PTR [...]" as an invalid opcode,
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// saying "64 bit operations are only supported in 64 bit modes." libopcodes
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// disassembles it as "fild DWORD PTR [...]", which is wrong. Workaround:
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// Output the raw opcode bytes instead of the instruction.
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//
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// gas intel_syntax mode treats "fistp QWORD PTR [...]" as an invalid opcode,
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// saying "64 bit operations are only supported in 64 bit modes." libopcodes
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// disassembles it as "fistpll DWORD PTR [...]", which is wrong. Workaround:
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// Output the raw opcode bytes instead of the instruction.
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switch (MI->getOpcode()) {
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case X86::FSTP80m:
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case X86::FLD80m:
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case X86::FILD64m:
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case X86::FISTP64m:
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GasBugWorkaroundEmitter gwe(O);
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X86::emitInstruction(gwe, (X86InstrInfo&)*TM.getInstrInfo(), *MI);
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O << "\t# ";
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}
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// Call the autogenerated instruction printer routines.
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bool Handled = printInstruction(MI);
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if (!Handled) {
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MI->dump();
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assert(0 && "Do not know how to print this instruction!");
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abort();
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}
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}
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bool X86IntelAsmPrinter::doInitialization(Module &M) {
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AsmPrinter::doInitialization(M);
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// Tell gas we are outputting Intel syntax (not AT&T syntax) assembly.
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//
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// Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an
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// instruction as a reference to the register named sp, and if you try to
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// reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased
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// before being looked up in the symbol table. This creates spurious
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// `undefined symbol' errors when linking. Workaround: Do not use `noprefix'
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// mode, and decorate all register names with percent signs.
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O << "\t.intel_syntax\n";
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return false;
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}
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// SwitchSection - Switch to the specified section of the executable if we are
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// not already in it!
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//
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static void SwitchSection(std::ostream &OS, std::string &CurSection,
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const char *NewSection) {
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if (CurSection != NewSection) {
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CurSection = NewSection;
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if (!CurSection.empty())
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OS << "\t" << NewSection << "\n";
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}
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}
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bool X86IntelAsmPrinter::doFinalization(Module &M) {
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const TargetData &TD = TM.getTargetData();
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std::string CurSection;
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// Print out module-level global variables here.
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for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I)
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if (I->hasInitializer()) { // External global require no code
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O << "\n\n";
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std::string name = Mang->getValueName(I);
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Constant *C = I->getInitializer();
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unsigned Size = TD.getTypeSize(C->getType());
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unsigned Align = TD.getTypeAlignmentShift(C->getType());
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if (C->isNullValue() &&
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(I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
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I->hasWeakLinkage() /* FIXME: Verify correct */)) {
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SwitchSection(O, CurSection, ".data");
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if (I->hasInternalLinkage())
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O << "\t.local " << name << "\n";
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O << "\t.comm " << name << "," << TD.getTypeSize(C->getType())
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<< "," << (1 << Align);
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O << "\t\t# ";
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WriteAsOperand(O, I, true, true, &M);
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O << "\n";
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} else {
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switch (I->getLinkage()) {
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case GlobalValue::LinkOnceLinkage:
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case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak.
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// Nonnull linkonce -> weak
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O << "\t.weak " << name << "\n";
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SwitchSection(O, CurSection, "");
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O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\",@progbits\n";
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break;
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case GlobalValue::AppendingLinkage:
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// FIXME: appending linkage variables should go into a section of
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// their name or something. For now, just emit them as external.
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case GlobalValue::ExternalLinkage:
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// If external or appending, declare as a global symbol
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O << "\t.globl " << name << "\n";
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// FALL THROUGH
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case GlobalValue::InternalLinkage:
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if (C->isNullValue())
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SwitchSection(O, CurSection, ".bss");
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else
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SwitchSection(O, CurSection, ".data");
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break;
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}
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emitAlignment(Align);
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O << "\t.type " << name << ",@object\n";
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O << "\t.size " << name << "," << Size << "\n";
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O << name << ":\t\t\t\t# ";
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WriteAsOperand(O, I, true, true, &M);
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O << " = ";
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WriteAsOperand(O, C, false, false, &M);
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O << "\n";
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emitGlobalConstant(C);
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}
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}
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AsmPrinter::doFinalization(M);
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return false; // success
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}
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