Tom Stellard 9a7e35aecc R600/SI: Avoid generating REGISTER_LOAD instructions. ... SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code path for 8-bit and 16-bit private loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214865 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-05 14:40:52 +00:00
..
Analysis
Assembler	verify-uselistorder: Change the default -num-shuffles=5	2014-07-31 18:46:24 +00:00
Bindings	[OCaml] Add Llvm.{string_of_const,const_element}.	2014-08-03 23:54:22 +00:00
Bitcode	UseListOrder: Fix blockaddress use-list order	2014-08-01 22:27:19 +00:00
BugPoint
CodeGen	R600/SI: Avoid generating REGISTER_LOAD instructions.	2014-08-05 14:40:52 +00:00
DebugInfo	Cleanup this test some more.	2014-08-01 23:01:32 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation	[ASan] Use metadata to pass source-level information from Clang to ASan.	2014-08-02 00:35:50 +00:00
Integer
JitListener
Linker
LTO
MC	Add dci/ici instructions for PPC 476 and friends.	2014-08-05 14:40:32 +00:00
Object
Other
TableGen	Allow binary and for tblgen math.	2014-08-05 09:43:25 +00:00
tools	InstrProf: Allow multiple functions with the same name	2014-08-01 22:50:07 +00:00
Transforms	Teach the SLP Vectorizer that keeping some values live over a callsite can have a cost.	2014-08-05 12:30:34 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh