mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7ac1609a3b
been MC-ized for assembly printing. MSP430 is mostly so, but still has the asm printer and lowering code in the printer subdir for the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
3.0 KiB
C++
96 lines
3.0 KiB
C++
//===-- X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an X86 MCInst to intel style .s file syntax.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86_INTEL_INST_PRINTER_H
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#define X86_INTEL_INST_PRINTER_H
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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class MCOperand;
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class X86IntelInstPrinter : public MCInstPrinter {
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public:
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X86IntelInstPrinter(const MCAsmInfo &MAI)
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: MCInstPrinter(MAI) {}
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virtual void printInst(const MCInst *MI, raw_ostream &OS);
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virtual StringRef getOpcodeName(unsigned Opcode) const;
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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static const char *getInstructionName(unsigned Opcode);
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
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void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O);
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void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "OPAQUE PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "BYTE PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "WORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "DWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "QWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "XMMWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "YMMWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "DWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "QWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "XWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "XMMWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "YMMWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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};
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}
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#endif
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