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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62036 91177308-0d34-0410-b5e6-96231b3b80d8
270 lines
9.7 KiB
C++
270 lines
9.7 KiB
C++
//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the ScheduleDAG class, which is a base class used by
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// scheduling implementation classes.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "llvm/CodeGen/ScheduleDAGSDNodes.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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ScheduleDAGSDNodes::ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
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const TargetMachine &tm)
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: ScheduleDAG(dag, bb, tm) {
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}
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SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
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SUnit *SU = NewSUnit(Old->getNode());
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SU->OrigNode = Old->OrigNode;
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SU->Latency = Old->Latency;
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SU->isTwoAddress = Old->isTwoAddress;
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SU->isCommutable = Old->isCommutable;
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SU->hasPhysRegDefs = Old->hasPhysRegDefs;
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return SU;
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}
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/// CheckForPhysRegDependency - Check if the dependency between def and use of
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/// a specified operand is a physical register dependency. If so, returns the
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/// register.
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static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
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const TargetRegisterInfo *TRI,
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const TargetInstrInfo *TII,
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unsigned &PhysReg) {
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if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
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return;
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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return;
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unsigned ResNo = User->getOperand(2).getResNo();
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if (Def->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
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if (ResNo >= II.getNumDefs() &&
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II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg)
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PhysReg = Reg;
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}
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}
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void ScheduleDAGSDNodes::BuildSchedUnits() {
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// During scheduling, the NodeId field of SDNode is used to map SDNodes
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// to their associated SUnits by holding SUnits table indices. A value
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// of -1 means the SDNode does not yet have an associated SUnit.
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unsigned NumNodes = 0;
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for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
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E = DAG->allnodes_end(); NI != E; ++NI) {
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NI->setNodeId(-1);
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++NumNodes;
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}
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// Reserve entries in the vector for each of the SUnits we are creating. This
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// ensure that reallocation of the vector won't happen, so SUnit*'s won't get
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// invalidated.
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// FIXME: Multiply by 2 because we may clone nodes during scheduling.
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// This is a temporary workaround.
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SUnits.reserve(NumNodes * 2);
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// Check to see if the scheduler cares about latencies.
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bool UnitLatencies = ForceUnitLatencies();
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for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
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E = DAG->allnodes_end(); NI != E; ++NI) {
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if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
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continue;
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// If this node has already been processed, stop now.
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if (NI->getNodeId() != -1) continue;
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SUnit *NodeSUnit = NewSUnit(NI);
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// See if anything is flagged to this node, if so, add them to flagged
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// nodes. Nodes can have at most one flag input and one flag output. Flags
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// are required the be the last operand and result of a node.
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// Scan up to find flagged preds.
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SDNode *N = NI;
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if (N->getNumOperands() &&
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N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
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do {
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N = N->getOperand(N->getNumOperands()-1).getNode();
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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} while (N->getNumOperands() &&
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N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
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}
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// Scan down to find any flagged succs.
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N = NI;
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while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
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SDValue FlagVal(N, N->getNumValues()-1);
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// There are either zero or one users of the Flag result.
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bool HasFlagUse = false;
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for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
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UI != E; ++UI)
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if (FlagVal.isOperandOf(*UI)) {
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HasFlagUse = true;
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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N = *UI;
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break;
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}
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if (!HasFlagUse) break;
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}
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// If there are flag operands involved, N is now the bottom-most node
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// of the sequence of nodes that are flagged together.
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// Update the SUnit.
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NodeSUnit->setNode(N);
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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// Assign the Latency field of NodeSUnit using target-provided information.
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if (UnitLatencies)
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NodeSUnit->Latency = 1;
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else
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ComputeLatency(NodeSUnit);
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}
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}
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void ScheduleDAGSDNodes::AddSchedEdges() {
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// Pass 2: add the preds, succs, etc.
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for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
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SUnit *SU = &SUnits[su];
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SDNode *MainNode = SU->getNode();
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if (MainNode->isMachineOpcode()) {
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unsigned Opc = MainNode->getMachineOpcode();
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const TargetInstrDesc &TID = TII->get(Opc);
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for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
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if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
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SU->isTwoAddress = true;
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break;
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}
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}
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if (TID.isCommutable())
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SU->isCommutable = true;
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}
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// Find all predecessors and successors of the group.
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for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
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if (N->isMachineOpcode() &&
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TII->get(N->getMachineOpcode()).getImplicitDefs() &&
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CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs())
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SU->hasPhysRegDefs = true;
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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SDNode *OpN = N->getOperand(i).getNode();
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if (isPassiveNode(OpN)) continue; // Not scheduled.
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SUnit *OpSU = &SUnits[OpN->getNodeId()];
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assert(OpSU && "Node has no SUnit!");
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if (OpSU == SU) continue; // In the same group.
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MVT OpVT = N->getOperand(i).getValueType();
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assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
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bool isChain = OpVT == MVT::Other;
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unsigned PhysReg = 0;
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// Determine if this is a physical register dependency.
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CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg);
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assert((PhysReg == 0 || !isChain) &&
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"Chain dependence via physreg data?");
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SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data,
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OpSU->Latency, PhysReg));
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}
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}
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}
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}
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/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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/// are input. This SUnit graph is similar to the SelectionDAG, but
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/// excludes nodes that aren't interesting to scheduling, and represents
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/// flagged together nodes with a single SUnit.
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void ScheduleDAGSDNodes::BuildSchedGraph() {
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// Populate the SUnits array.
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BuildSchedUnits();
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// Compute all the scheduling dependencies between nodes.
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AddSchedEdges();
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}
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void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
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const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
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// Compute the latency for the node. We use the sum of the latencies for
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// all nodes flagged together into this SUnit.
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SU->Latency = 0;
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bool SawMachineOpcode = false;
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for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
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if (N->isMachineOpcode()) {
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SawMachineOpcode = true;
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SU->Latency +=
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InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
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}
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}
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands (which do
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/// not go into the resulting MachineInstr).
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unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
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unsigned N = Node->getNumValues();
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while (N && Node->getValueType(N - 1) == MVT::Flag)
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--N;
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if (N && Node->getValueType(N - 1) == MVT::Other)
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--N; // Skip over chain result.
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return N;
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}
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/// CountOperands - The inputs to target nodes have any actual inputs first,
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/// followed by special operands that describe memory references, then an
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/// optional chain operand, then an optional flag operand. Compute the number
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/// of actual operands that will go into the resulting MachineInstr.
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unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
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unsigned N = ComputeMemOperandsEnd(Node);
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while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
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--N; // Ignore MEMOPERAND nodes
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return N;
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}
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/// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
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/// operand
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unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
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unsigned N = Node->getNumOperands();
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while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
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--N;
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if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
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--N; // Ignore chain if it exists.
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return N;
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}
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void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
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if (SU->getNode())
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SU->getNode()->dump(DAG);
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else
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cerr << "CROSS RC COPY ";
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cerr << "\n";
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SmallVector<SDNode *, 4> FlaggedNodes;
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for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
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FlaggedNodes.push_back(N);
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while (!FlaggedNodes.empty()) {
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cerr << " ";
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FlaggedNodes.back()->dump(DAG);
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cerr << "\n";
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FlaggedNodes.pop_back();
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}
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}
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