mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
369cc938d2
This is a complete re-write if the bottom-up vectorization class. Before this commit we scanned the instruction tree 3 times. First in search of merge points for the trees. Second, for estimating the cost. And finally for vectorization. There was a lot of code duplication and adding the DCE exposed bugs. The new design is simpler and DCE was a part of the design. In this implementation we build the tree once. After that we estimate the cost by scanning the different entries in the constructed tree (in any order). The vectorization phase also works on the built tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185774 91177308-0d34-0410-b5e6-96231b3b80d8
114 lines
5.2 KiB
LLVM
114 lines
5.2 KiB
LLVM
; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.8.0"
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%struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171 = type { i32, i32, i32, i32, i32, i32, [8 x i8] }
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define void @SIM4() {
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entry:
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br i1 undef, label %return, label %lor.lhs.false
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lor.lhs.false: ; preds = %entry
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br i1 undef, label %return, label %if.end
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if.end: ; preds = %lor.lhs.false
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br i1 undef, label %for.end605, label %for.body.lr.ph
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for.body.lr.ph: ; preds = %if.end
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br label %for.body
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for.body: ; preds = %for.inc603, %for.body.lr.ph
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br i1 undef, label %for.inc603, label %if.end12
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if.end12: ; preds = %for.body
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br i1 undef, label %land.lhs.true, label %land.lhs.true167
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land.lhs.true: ; preds = %if.end12
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br i1 undef, label %if.then17, label %land.lhs.true167
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if.then17: ; preds = %land.lhs.true
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br i1 undef, label %if.end98, label %land.rhs.lr.ph
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land.rhs.lr.ph: ; preds = %if.then17
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unreachable
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if.end98: ; preds = %if.then17
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%from299 = getelementptr inbounds %struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171* undef, i64 0, i32 1
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br i1 undef, label %land.lhs.true167, label %if.then103
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if.then103: ; preds = %if.end98
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%.sub100 = select i1 undef, i32 250, i32 undef
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%mul114 = shl nsw i32 %.sub100, 2
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%from1115 = getelementptr inbounds %struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171* undef, i64 0, i32 0
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%cond125 = select i1 undef, i32 undef, i32 %mul114
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br label %for.cond.i
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for.cond.i: ; preds = %land.rhs.i874, %if.then103
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%row.0.i = phi i32 [ undef, %land.rhs.i874 ], [ %.sub100, %if.then103 ]
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%col.0.i = phi i32 [ undef, %land.rhs.i874 ], [ %cond125, %if.then103 ]
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br i1 undef, label %land.rhs.i874, label %for.end.i
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land.rhs.i874: ; preds = %for.cond.i
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br i1 undef, label %for.cond.i, label %for.end.i
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for.end.i: ; preds = %land.rhs.i874, %for.cond.i
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br i1 undef, label %if.then.i, label %if.end.i
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if.then.i: ; preds = %for.end.i
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%add14.i = add nsw i32 %row.0.i, undef
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%add15.i = add nsw i32 %col.0.i, undef
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br label %extend_bw.exit
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if.end.i: ; preds = %for.end.i
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%add16.i = add i32 %cond125, %.sub100
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%cmp26514.i = icmp slt i32 %add16.i, 0
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br i1 %cmp26514.i, label %for.end33.i, label %for.body28.lr.ph.i
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for.body28.lr.ph.i: ; preds = %if.end.i
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br label %for.end33.i
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for.end33.i: ; preds = %for.body28.lr.ph.i, %if.end.i
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br i1 undef, label %for.end58.i, label %for.body52.lr.ph.i
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for.body52.lr.ph.i: ; preds = %for.end33.i
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br label %for.end58.i
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for.end58.i: ; preds = %for.body52.lr.ph.i, %for.end33.i
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br label %while.cond260.i
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while.cond260.i: ; preds = %land.rhs263.i, %for.end58.i
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br i1 undef, label %land.rhs263.i, label %while.end275.i
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land.rhs263.i: ; preds = %while.cond260.i
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br i1 undef, label %while.cond260.i, label %while.end275.i
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while.end275.i: ; preds = %land.rhs263.i, %while.cond260.i
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br label %extend_bw.exit
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extend_bw.exit: ; preds = %while.end275.i, %if.then.i
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%add14.i1262 = phi i32 [ %add14.i, %if.then.i ], [ undef, %while.end275.i ]
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%add15.i1261 = phi i32 [ %add15.i, %if.then.i ], [ undef, %while.end275.i ]
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br i1 false, label %if.then157, label %land.lhs.true167
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if.then157: ; preds = %extend_bw.exit
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%add158 = add nsw i32 %add14.i1262, 1
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store i32 %add158, i32* %from299, align 4
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%add160 = add nsw i32 %add15.i1261, 1
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store i32 %add160, i32* %from1115, align 4
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br label %land.lhs.true167
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land.lhs.true167: ; preds = %if.then157, %extend_bw.exit, %if.end98, %land.lhs.true, %if.end12
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unreachable
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for.inc603: ; preds = %for.body
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br i1 undef, label %for.body, label %for.end605
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for.end605: ; preds = %for.inc603, %if.end
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unreachable
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return: ; preds = %lor.lhs.false, %entry
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ret void
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}
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