mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-19 01:13:25 +00:00
9ade218533
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29898 91177308-0d34-0410-b5e6-96231b3b80d8
518 lines
17 KiB
C++
518 lines
17 KiB
C++
//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the ARM target.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMTargetMachine.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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#include <queue>
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#include <set>
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using namespace llvm;
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namespace {
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class ARMTargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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public:
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ARMTargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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};
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}
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ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass);
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//LLVM requires that a register class supports MVT::f64!
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addRegisterClass(MVT::f64, ARM::IntRegsRegisterClass);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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setSchedulingPreference(SchedulingForRegPressure);
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computeRegisterProperties();
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}
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namespace llvm {
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namespace ARMISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
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/// CALL - A direct function call.
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CALL,
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/// Return with a flag operand.
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RET_FLAG,
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CMP,
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SELECT,
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BR
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};
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}
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}
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/// DAGCCToARMCC - Convert a DAG integer condition code to an ARM CC
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static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code!");
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case ISD::SETNE: return ARMCC::NE;
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case ISD::SETEQ: return ARMCC::EQ;
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}
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}
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const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case ARMISD::CALL: return "ARMISD::CALL";
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case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
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case ARMISD::SELECT: return "ARMISD::SELECT";
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case ARMISD::CMP: return "ARMISD::CMP";
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case ARMISD::BR: return "ARMISD::BR";
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}
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}
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// This transforms a ISD::CALL node into a
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// callseq_star <- ARMISD:CALL <- callseq_end
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// chain
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static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Chain = Op.getOperand(0);
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unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
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assert(CallConv == CallingConv::C && "unknown calling convention");
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
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assert(isTailCall == false && "tail call not supported");
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SDOperand Callee = Op.getOperand(4);
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unsigned NumOps = (Op.getNumOperands() - 5) / 2;
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// Count how many bytes are to be pushed on the stack.
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unsigned NumBytes = 0;
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// Add up all the space actually used.
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for (unsigned i = 4; i < NumOps; ++i)
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NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
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// Adjust the stack pointer for the new arguments...
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// These operations are automatically eliminated by the prolog/epilog pass
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Chain = DAG.getCALLSEQ_START(Chain,
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DAG.getConstant(NumBytes, MVT::i32));
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SDOperand StackPtr = DAG.getRegister(ARM::R13, MVT::i32);
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static const unsigned int num_regs = 4;
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static const unsigned regs[num_regs] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3
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};
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std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
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std::vector<SDOperand> MemOpChains;
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for (unsigned i = 0; i != NumOps; ++i) {
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SDOperand Arg = Op.getOperand(5+2*i);
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assert(Arg.getValueType() == MVT::i32);
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if (i < num_regs)
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RegsToPass.push_back(std::make_pair(regs[i], Arg));
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else {
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unsigned ArgOffset = (i - num_regs) * 4;
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SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
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PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Arg, PtrOff, DAG.getSrcValue(NULL)));
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}
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}
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token chain
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// and flag operands which copy the outgoing args into the appropriate regs.
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SDOperand InFlag;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
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InFlag);
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InFlag = Chain.getValue(1);
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}
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std::vector<MVT::ValueType> NodeTys;
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NodeTys.push_back(MVT::Other); // Returns a chain
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NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
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// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
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// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
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// node so that legalize doesn't hack it.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
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// If this is a direct call, pass the chain and the callee.
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assert (Callee.Val);
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are known live
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// into the call.
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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RegsToPass[i].second.getValueType()));
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unsigned CallOpc = ARMISD::CALL;
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if (InFlag.Val)
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Ops.push_back(InFlag);
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Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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std::vector<SDOperand> ResultVals;
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NodeTys.clear();
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// If the call has results, copy the values out of the ret val registers.
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switch (Op.Val->getValueType(0)) {
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default: assert(0 && "Unexpected ret value!");
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case MVT::Other:
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break;
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case MVT::i32:
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Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
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ResultVals.push_back(Chain.getValue(0));
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NodeTys.push_back(MVT::i32);
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}
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
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DAG.getConstant(NumBytes, MVT::i32));
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NodeTys.push_back(MVT::Other);
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if (ResultVals.empty())
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return Chain;
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ResultVals.push_back(Chain);
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SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
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ResultVals.size());
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return Res.getValue(Op.ResNo);
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}
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static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Copy;
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SDOperand Chain = Op.getOperand(0);
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switch(Op.getNumOperands()) {
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default:
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assert(0 && "Do not know how to return this many arguments!");
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abort();
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case 1: {
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SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
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return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
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}
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case 3:
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Copy = DAG.getCopyToReg(Chain, ARM::R0, Op.getOperand(1), SDOperand());
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if (DAG.getMachineFunction().liveout_empty())
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DAG.getMachineFunction().addLiveOut(ARM::R0);
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break;
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}
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//We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
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return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
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}
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static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
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unsigned *vRegs,
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unsigned ArgNo) {
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MachineFunction &MF = DAG.getMachineFunction();
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MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
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assert (ObjectVT == MVT::i32);
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SDOperand Root = Op.getOperand(0);
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SSARegMap *RegMap = MF.getSSARegMap();
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unsigned num_regs = 4;
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static const unsigned REGS[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3
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};
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if(ArgNo < num_regs) {
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unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
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MF.addLiveIn(REGS[ArgNo], VReg);
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vRegs[ArgNo] = VReg;
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return DAG.getCopyFromReg(Root, VReg, MVT::i32);
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} else {
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// If the argument is actually used, emit a load from the right stack
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// slot.
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if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
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unsigned ArgOffset = (ArgNo - num_regs) * 4;
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MachineFrameInfo *MFI = MF.getFrameInfo();
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unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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return DAG.getLoad(ObjectVT, Root, FIN,
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DAG.getSrcValue(NULL));
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} else {
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// Don't emit a dead load.
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return DAG.getNode(ISD::UNDEF, ObjectVT);
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}
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}
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}
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static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType PtrVT = Op.getValueType();
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ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
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Constant *C = CP->get();
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SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
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return CPI;
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}
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static SDOperand LowerGlobalAddress(SDOperand Op,
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SelectionDAG &DAG) {
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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int alignment = 2;
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SDOperand CPAddr = DAG.getConstantPool(GV, MVT::i32, alignment);
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return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr,
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DAG.getSrcValue(NULL));
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}
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static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
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unsigned VarArgsFrameIndex) {
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// vastart just stores the address of the VarArgsFrameIndex slot into the
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// memory location argument.
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MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
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return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
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Op.getOperand(1), Op.getOperand(2));
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}
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static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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int &VarArgsFrameIndex) {
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std::vector<SDOperand> ArgValues;
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SDOperand Root = Op.getOperand(0);
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unsigned VRegs[4];
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unsigned NumArgs = Op.Val->getNumValues()-1;
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for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) {
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SDOperand ArgVal = LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo);
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ArgValues.push_back(ArgVal);
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}
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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if (isVarArg) {
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MachineFunction &MF = DAG.getMachineFunction();
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SSARegMap *RegMap = MF.getSSARegMap();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
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-16 + NumArgs * 4);
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static const unsigned REGS[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3
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};
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// If this function is vararg, store r0-r3 to their spots on the stack
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// so that they may be loaded by deferencing the result of va_next.
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SmallVector<SDOperand, 4> MemOps;
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for (unsigned ArgNo = 0; ArgNo < 4; ++ArgNo) {
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int ArgOffset = - (4 - ArgNo) * 4;
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
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ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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unsigned VReg;
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if (ArgNo < NumArgs)
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VReg = VRegs[ArgNo];
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else
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VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
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if (ArgNo >= NumArgs)
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MF.addLiveIn(REGS[ArgNo], VReg);
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SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
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Val, FIN, DAG.getSrcValue(NULL));
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MemOps.push_back(Store);
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}
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
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}
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ArgValues.push_back(Root);
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// Return the new list of results.
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std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
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Op.Val->value_end());
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return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
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}
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static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand LHS = Op.getOperand(0);
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SDOperand RHS = Op.getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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SDOperand TrueVal = Op.getOperand(2);
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SDOperand FalseVal = Op.getOperand(3);
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SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
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SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
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return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, ARMCC, Cmp);
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}
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static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Chain = Op.getOperand(0);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
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SDOperand LHS = Op.getOperand(2);
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SDOperand RHS = Op.getOperand(3);
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SDOperand Dest = Op.getOperand(4);
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SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
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SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
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return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
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}
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SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default:
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assert(0 && "Should not custom lower this!");
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abort();
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case ISD::ConstantPool:
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return LowerConstantPool(Op, DAG);
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case ISD::GlobalAddress:
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return LowerGlobalAddress(Op, DAG);
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case ISD::FORMAL_ARGUMENTS:
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return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
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case ISD::CALL:
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return LowerCALL(Op, DAG);
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case ISD::RET:
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return LowerRET(Op, DAG);
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case ISD::SELECT_CC:
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return LowerSELECT_CC(Op, DAG);
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case ISD::BR_CC:
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return LowerBR_CC(Op, DAG);
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case ISD::VASTART:
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return LowerVASTART(Op, DAG, VarArgsFrameIndex);
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}
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}
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// ARMDAGToDAGISel - ARM specific code to select ARM machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class ARMDAGToDAGISel : public SelectionDAGISel {
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ARMTargetLowering Lowering;
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public:
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ARMDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(Lowering), Lowering(TM) {
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}
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SDNode *Select(SDOperand Op);
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
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// Include the pieces autogenerated from the target description.
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#include "ARMGenDAGISel.inc"
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};
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void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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ScheduleAndEmitDAG(DAG);
|
|
}
|
|
|
|
static bool isInt12Immediate(SDNode *N, short &Imm) {
|
|
if (N->getOpcode() != ISD::Constant)
|
|
return false;
|
|
|
|
int32_t t = cast<ConstantSDNode>(N)->getValue();
|
|
int max = 2<<12 - 1;
|
|
int min = -max;
|
|
if (t > min && t < max) {
|
|
Imm = t;
|
|
return true;
|
|
}
|
|
else
|
|
return false;
|
|
}
|
|
|
|
static bool isInt12Immediate(SDOperand Op, short &Imm) {
|
|
return isInt12Immediate(Op.Val, Imm);
|
|
}
|
|
|
|
//register plus/minus 12 bit offset
|
|
bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
|
|
SDOperand &Base) {
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
if (N.getOpcode() == ISD::ADD) {
|
|
short imm = 0;
|
|
if (isInt12Immediate(N.getOperand(1), imm)) {
|
|
Offset = CurDAG->getTargetConstant(imm, MVT::i32);
|
|
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
|
|
Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
|
|
} else {
|
|
Base = N.getOperand(0);
|
|
}
|
|
return true; // [r+i]
|
|
}
|
|
}
|
|
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
|
|
Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
|
|
}
|
|
else
|
|
Base = N;
|
|
return true; //any address fits in a register
|
|
}
|
|
|
|
SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
|
|
SDNode *N = Op.Val;
|
|
|
|
switch (N->getOpcode()) {
|
|
default:
|
|
return SelectCode(Op);
|
|
break;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
} // end anonymous namespace
|
|
|
|
/// createARMISelDag - This pass converts a legalized DAG into a
|
|
/// ARM-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
|
|
return new ARMDAGToDAGISel(TM);
|
|
}
|