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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-23 15:29:51 +00:00
64d80e3387
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
2.3 KiB
TableGen
81 lines
2.3 KiB
TableGen
//===- IA64InstrFormats.td - IA64 Instruction Formats --*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Duraid Madina and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// - Warning: the stuff in here isn't really being used, so is mostly
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// junk. It'll get fixed as the JIT gets built.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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class InstIA64<bits<4> op, dag OOL, dag IOL, string asmstr> : Instruction {
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// IA64 instruction baseline
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field bits<41> Inst;
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let Namespace = "IA64";
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let OutOperandList = OOL;
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let InOperandList = IOL;
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let AsmString = asmstr;
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let Inst{40-37} = op;
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}
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//"Each Itanium instruction is categorized into one of six types."
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//We should have:
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// A, I, M, F, B, L+X
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class AForm<bits<4> opcode, bits<6> qpReg, dag OOL, dag IOL, string asmstr> :
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InstIA64<opcode, OOL, IOL, asmstr> {
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let Inst{5-0} = qpReg;
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}
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class AForm_DAG<bits<4> opcode, bits<6> qpReg, dag OOL, dag IOL, string asmstr,
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list<dag> pattern> :
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InstIA64<opcode, OOL, IOL, asmstr> {
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let Pattern = pattern;
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let Inst{5-0} = qpReg;
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}
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let isBranch = 1, isTerminator = 1 in
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class BForm<bits<4> opcode, bits<6> x6, bits<3> btype, dag OOL, dag IOL, string asmstr> :
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InstIA64<opcode, OOL, IOL, asmstr> {
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let Inst{32-27} = x6;
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let Inst{8-6} = btype;
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}
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class MForm<bits<4> opcode, bits<6> x6, dag OOL, dag IOL, string asmstr> :
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InstIA64<opcode, OOL, IOL, asmstr> {
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bits<7> Ra;
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bits<7> Rb;
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bits<16> disp;
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let Inst{35-30} = x6;
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// let Inst{20-16} = Rb;
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let Inst{15-0} = disp;
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}
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class RawForm<bits<4> opcode, bits<26> rest, dag OOL, dag IOL, string asmstr> :
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InstIA64<opcode, OOL, IOL, asmstr> {
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let Inst{25-0} = rest;
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}
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// Pseudo instructions.
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class PseudoInstIA64<dag OOL, dag IOL, string nm> : InstIA64<0, OOL, IOL, nm> {
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}
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class PseudoInstIA64_DAG<dag OOL, dag IOL, string nm, list<dag> pattern>
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: InstIA64<0, OOL, IOL, nm> {
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let Pattern = pattern;
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}
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