Misha Brukman 9b03633265 Because the format of the shift instructions is `shift r, shcnt, r', the ... instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that implies that the two registers are the first two parameters to the instruction. Thus I made the instructions inherit from F3rd again, and manually added an rs1 field AFTER the shcnt field in the instruction, which maps to the appropriate place in the instruction. The other changes are just elimination of unnecessary spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6437 91177308-0d34-0410-b5e6-96231b3b80d8		2003-05-30 18:06:10 +00:00
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CBackend	Eliminate unnecessary ->get calls that are now automatically handled.	2003-05-29 15:12:27 +00:00
SparcV9	Because the format of the shift instructions is `shift r, shcnt, r', the	2003-05-30 18:06:10 +00:00
X86	Renamed opIsDef to opIsDefOnly.	2003-05-27 00:03:17 +00:00
Makefile	X86 target builds fine now	2002-11-20 20:17:03 +00:00
MRegisterInfo.cpp	Capture more information in ctor	2002-12-28 20:34:18 +00:00
Target.td	Added the target-independent part of TableGen data.	2003-05-29 18:48:17 +00:00
TargetData.cpp	* Fix divide by zero error with empty structs	2003-05-21 18:08:44 +00:00
TargetInstrInfo.cpp	Rename MachineInstrInfo -> TargetInstrInfo	2003-01-14 22:00:31 +00:00
TargetMachine.cpp	The promotion rules are the same for all targets, they are set by the C standard.	2003-04-26 19:47:36 +00:00
TargetSchedInfo.cpp	More renamings of Target/Machine*Info to Target/Target*Info	2002-12-29 03:13:05 +00:00