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527388dea5
PPC64 target. The five tests modified herein test code generation that is sensitive to the code model selected. So I've added -code-model=small to the RUN commands for each. Since small code model is the default, this has no effect for now; but this prepares us for eventually changing the default to medium code model for PPC64. Test changes verified with small and medium code model as default on powerpc64-unknown-linux-gnu. All tests continue to pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167999 91177308-0d34-0410-b5e6-96231b3b80d8
156 lines
4.2 KiB
LLVM
156 lines
4.2 KiB
LLVM
; RUN: llc -mcpu=pwr6 -mattr=+altivec -code-model=small < %s | FileCheck %s
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; Check vector extend load expansion with altivec enabled.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Altivec does not provides an sext intruction, so it expands
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; a set of vector stores (stvx), bytes load/sign expand/store
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; (lbz/stb), and a final vector load (lvx) to load the result
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; extended vector.
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define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {
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%b = trunc <16 x i8> %a to <16 x i4>
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%c = sext <16 x i4> %b to <16 x i8>
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ret <16 x i8> %c
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}
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; CHECK: v16si8_sext_in_reg:
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lbz
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; CHECK: stb
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; CHECK: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; The zero extend uses a more clever logic: a vector splat
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; and a logic and to set higher bits to 0.
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define <16 x i8> @v16si8_zext_in_reg(<16 x i8> %a) {
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%b = trunc <16 x i8> %a to <16 x i4>
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%c = zext <16 x i4> %b to <16 x i8>
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ret <16 x i8> %c
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}
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; CHECK: v16si8_zext_in_reg:
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; CHECK: vspltisb [[VMASK:[0-9]+]], 15
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; CHECK-NEXT: vand 2, 2, [[VMASK]]
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; Same as v16si8_sext_in_reg, expands to load/store halfwords (lhz/sth).
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define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
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%b = trunc <8 x i16> %a to <8 x i8>
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%c = sext <8 x i8> %b to <8 x i16>
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ret <8 x i16> %c
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}
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; CHECK: v8si16_sext_in_reg:
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lhz
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; CHECK: sth
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; CHECK: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; Same as v8si16_sext_in_reg, but instead of creating the mask
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; with a splat, loads it from memory.
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define <8 x i16> @v8si16_zext_in_reg(<8 x i16> %a) {
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%b = trunc <8 x i16> %a to <8 x i8>
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%c = zext <8 x i8> %b to <8 x i16>
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ret <8 x i16> %c
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}
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; CHECK: v8si16_zext_in_reg:
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; CHECK: ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2)
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; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]]
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; CHECK-NEXT: vand 2, 2, [[VMASK]]
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; Same as v16si8_sext_in_reg, expands to load halfword (lha) and
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; store words (stw).
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define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {
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%b = trunc <4 x i32> %a to <4 x i16>
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%c = sext <4 x i16> %b to <4 x i32>
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ret <4 x i32> %c
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}
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; CHECK: v4si32_sext_in_reg:
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lha
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; CHECK: stw
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lha
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; CHECK: stw
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lha
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; CHECK: stw
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; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: lha
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; CHECK: stw
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; CHECK: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; Same as v8si16_sext_in_reg.
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define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) {
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%b = trunc <4 x i32> %a to <4 x i16>
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%c = zext <4 x i16> %b to <4 x i32>
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ret <4 x i32> %c
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}
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; CHECK: v4si32_zext_in_reg:
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; CHECK: vspltisw [[VMASK:[0-9]+]], -16
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; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]]
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; CHECK-NEXT: vand 2, 2, [[VMASK]]
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