mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-28 22:29:56 +00:00
435b9bd9fb
This patch is a supplement of implementing predicate of FP, enabling aarch64 backend no-fp tests on arm64 target for verification. During this, one bug is exposed and fixed by this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207215 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
2.6 KiB
LLVM
95 lines
2.6 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
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; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
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define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
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; CHECK-LABEL: test_select_i32:
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%val = select i1 %bit, i32 %a, i32 %b
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; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
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; CHECK-AARCH64: tst w0, [[ONE]]
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; CHECK-ARM64: tst w0, #0x1
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; CHECK-NEXT: csel w0, w1, w2, ne
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ret i32 %val
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}
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define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
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; CHECK-LABEL: test_select_i64:
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%val = select i1 %bit, i64 %a, i64 %b
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; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
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; CHECK-AARCH64: tst w0, [[ONE]]
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; CHECK-ARM64: tst w0, #0x1
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; CHECK-NEXT: csel x0, x1, x2, ne
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ret i64 %val
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}
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define float @test_select_float(i1 %bit, float %a, float %b) {
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; CHECK-LABEL: test_select_float:
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%val = select i1 %bit, float %a, float %b
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; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
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; CHECK-AARCH64: tst w0, [[ONE]]
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; CHECK-ARM64: tst w0, #0x1
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; CHECK-NEXT: fcsel s0, s0, s1, ne
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; CHECK-NOFP-NOT: fcsel
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ret float %val
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}
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define double @test_select_double(i1 %bit, double %a, double %b) {
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; CHECK-LABEL: test_select_double:
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%val = select i1 %bit, double %a, double %b
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; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
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; CHECK-AARCH64: tst w0, [[ONE]]
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; CHECK-ARM64: tst w0, #0x1
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; CHECK-NEXT: fcsel d0, d0, d1, ne
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; CHECK-NOFP-NOT: fcsel
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ret double %val
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}
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define i32 @test_brcond(i1 %bit) {
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; CHECK-LABEL: test_brcond:
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br i1 %bit, label %true, label %false
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; CHECK: tbz {{w[0-9]+}}, #0, {{.?LBB}}
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true:
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ret i32 0
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false:
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ret i32 42
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}
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define i1 @test_setcc_float(float %lhs, float %rhs) {
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; CHECK: test_setcc_float
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%val = fcmp oeq float %lhs, %rhs
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; CHECK: fcmp s0, s1
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; CHECK: csinc w0, wzr, wzr, ne
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; CHECK-NOFP-NOT: fcmp
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ret i1 %val
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}
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define i1 @test_setcc_double(double %lhs, double %rhs) {
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; CHECK: test_setcc_double
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%val = fcmp oeq double %lhs, %rhs
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; CHECK: fcmp d0, d1
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; CHECK: csinc w0, wzr, wzr, ne
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; CHECK-NOFP-NOT: fcmp
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ret i1 %val
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}
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define i1 @test_setcc_i32(i32 %lhs, i32 %rhs) {
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; CHECK: test_setcc_i32
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%val = icmp ugt i32 %lhs, %rhs
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, ls
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ret i1 %val
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}
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define i1 @test_setcc_i64(i64 %lhs, i64 %rhs) {
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; CHECK: test_setcc_i64
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%val = icmp ne i64 %lhs, %rhs
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; CHECK: cmp x0, x1
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; CHECK: csinc w0, wzr, wzr, eq
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ret i1 %val
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}
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