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43705683fd
There are no patterns for this. This was already fixed for ARM64 but I forgot to apply it to AArch64 too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207515 91177308-0d34-0410-b5e6-96231b3b80d8
15 lines
390 B
LLVM
15 lines
390 B
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
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; RUN: llc -mtriple=arm64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
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define <4 x i32> @test1(<4 x i32> %a) {
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%rem = srem <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %rem
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; CHECK-LABEL: test1
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; FIXME: Can we lower this more efficiently?
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; CHECK: mul
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; CHECK: mul
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; CHECK: mul
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; CHECK: mul
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}
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