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This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8 |
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|---|---|---|
| .. | ||
| AsmParser | ||
| Disassembler | ||
| InstPrinter | ||
| MCTargetDesc | ||
| TargetInfo | ||
| Utils | ||
| AArch64.h | ||
| AArch64.td | ||
| AArch64AsmPrinter.cpp | ||
| AArch64AsmPrinter.h | ||
| AArch64BranchFixupPass.cpp | ||
| AArch64CallingConv.td | ||
| AArch64FrameLowering.cpp | ||
| AArch64FrameLowering.h | ||
| AArch64InstrFormats.td | ||
| AArch64InstrInfo.cpp | ||
| AArch64InstrInfo.h | ||
| AArch64InstrInfo.td | ||
| AArch64ISelDAGToDAG.cpp | ||
| AArch64ISelLowering.cpp | ||
| AArch64ISelLowering.h | ||
| AArch64MachineFunctionInfo.cpp | ||
| AArch64MachineFunctionInfo.h | ||
| AArch64MCInstLower.cpp | ||
| AArch64RegisterInfo.cpp | ||
| AArch64RegisterInfo.h | ||
| AArch64RegisterInfo.td | ||
| AArch64Schedule.td | ||
| AArch64SelectionDAGInfo.cpp | ||
| AArch64SelectionDAGInfo.h | ||
| AArch64Subtarget.cpp | ||
| AArch64Subtarget.h | ||
| AArch64TargetMachine.cpp | ||
| AArch64TargetMachine.h | ||
| AArch64TargetObjectFile.cpp | ||
| AArch64TargetObjectFile.h | ||
| CMakeLists.txt | ||
| LLVMBuild.txt | ||
| Makefile | ||
| README.txt | ||
This file will contain changes that need to be made before AArch64 can become an officially supported target. Currently a placeholder.