mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-31 12:30:06 +00:00
dd950096b9
- Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we need to ensure that i128 is 16-byte aligned in real life), and 128 zero- extends are supported. - New td file: SPU128InstrInfo.td: this is where all new i128 support should be put in the future. - Continue to hammer on i64 operations and test cases; ensure that the only remaining problem will be i64 mul. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61784 91177308-0d34-0410-b5e6-96231b3b80d8
243 lines
8.7 KiB
TableGen
243 lines
8.7 KiB
TableGen
//====--- SPU64InstrInfo.td - Cell SPU 64-bit operations -*- tablegen -*--====//
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//
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// Cell SPU 64-bit operations
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//
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// Primary author: Scott Michel (scottm@aero.org)
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//===----------------------------------------------------------------------===//
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// 64-bit comparisons:
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//
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// 1. The instruction sequences for vector vice scalar differ by a
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// constant. In the scalar case, we're only interested in the
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// top two 32-bit slots, whereas we're interested in an exact
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// all-four-slot match in the vector case.
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//
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// 2. There are no "immediate" forms, since loading 64-bit constants
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// could be a constant pool load.
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//
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// 3. i64 setcc results are i32, which are subsequently converted to a FSM
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// mask when used in a select pattern.
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//
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// 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO)
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// [Note: this may be moot, since gb produces v4i32 or r32.]
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//
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// 5. The code sequences for r64 and v2i64 are probably overly conservative,
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// compared to the code that gcc produces.
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//
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// M00$E B!tes Kan be Pretty N@sTi!!!!! (appologies to Monty!)
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// selb instruction definition for i64. Note that the selection mask is
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// a vector, produced by various forms of FSM:
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def SELBr64_cond:
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SELBInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB, VECREG:$rC),
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[/* no pattern */]>;
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// select the negative condition:
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class I64SELECTNegCond<PatFrag cond, CodeFrag compare>:
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Pat<(select (i32 (cond R64C:$rA, R64C:$rB)), R64C:$rTrue, R64C:$rFalse),
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(SELBr64_cond R64C:$rTrue, R64C:$rFalse, (FSMr32 compare.Fragment))>;
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// setcc the negative condition:
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class I64SETCCNegCond<PatFrag cond, CodeFrag compare>:
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Pat<(cond R64C:$rA, R64C:$rB),
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(XORIr32 compare.Fragment, -1)>;
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// The generic i64 select pattern, which assumes that the comparison result
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// is in a 32-bit register that contains a select mask pattern (i.e., gather
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// bits result):
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def : Pat<(select R32C:$rCond, R64C:$rFalse, R64C:$rTrue),
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(SELBr64_cond R64C:$rTrue, R64C:$rFalse, (FSMr32 R32C:$rCond))>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// The i64 seteq fragment that does the scalar->vector conversion and
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// comparison:
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def CEQr64compare:
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CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (ORv2i64_i64 R64C:$rA),
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(ORv2i64_i64 R64C:$rB))), 0xb)>;
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// The i64 seteq fragment that does the vector comparison
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def CEQv2i64compare:
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CodeFrag<(CEQIv4i32 (GBv4i32 (CEQv4i32 VECREG:$rA, VECREG:$rB)), 0xf)>;
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// i64 seteq (equality): the setcc result is i32, which is converted to a
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// vector FSM mask when used in a select pattern.
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//
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// v2i64 seteq (equality): the setcc result is v4i32
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multiclass CompareEqual64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(ORi32_v4i32 CEQr64compare.Fragment)>;
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def v2i64: CodeFrag<(ORi32_v4i32 CEQv2i64compare.Fragment)>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CEQr64compare.Fragment))>;
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def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CEQv2i64compare.Fragment))>;
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}
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defm I64EQ: CompareEqual64;
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def : Pat<(seteq R64C:$rA, R64C:$rB), I64EQr64.Fragment>;
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def : Pat<(seteq (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), I64EQv2i64.Fragment>;
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// i64 setne:
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def : I64SETCCNegCond<setne, I64EQr64>;
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def : I64SELECTNegCond<setne, I64EQr64>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// i64 setugt/setule:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def CLGTr64ugt:
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CodeFrag<(CLGTv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>;
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def CLGTr64eq:
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CodeFrag<(CEQv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>;
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def CLGTr64compare:
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CodeFrag<(SELBv2i64 CLGTr64ugt.Fragment,
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(XSWDv2i64 CLGTr64ugt.Fragment),
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CLGTr64eq.Fragment)>;
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def CLGTv2i64ugt:
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CodeFrag<(CLGTv4i32 VECREG:$rA, VECREG:$rB)>;
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def CLGTv2i64eq:
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CodeFrag<(CEQv4i32 VECREG:$rA, VECREG:$rB)>;
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def CLGTv2i64compare:
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CodeFrag<(SELBv2i64 CLGTv2i64ugt.Fragment,
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(XSWDv2i64 CLGTr64ugt.Fragment),
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CLGTv2i64eq.Fragment)>;
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multiclass CompareLogicalGreaterThan64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(ORi32_v4i32 CLGTr64compare.Fragment)>;
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def v2i64: CodeFrag<CLGTv2i64compare.Fragment>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGTr64compare.Fragment))>;
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def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGTv2i64compare.Fragment))>;
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}
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defm I64LGT: CompareLogicalGreaterThan64;
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def : Pat<(setugt R64C:$rA, R64C:$rB), I64LGTr64.Fragment>;
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def : Pat<(setugt (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
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I64LGTv2i64.Fragment>;
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// i64 setult:
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def : I64SETCCNegCond<setule, I64LGTr64>;
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def : I64SELECTNegCond<setule, I64LGTr64>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// i64 setuge/setult:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def CLGEr64compare:
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CodeFrag<(CGTIv4i32 (GBv4i32 (ORv4i32 CLGTr64ugt.Fragment,
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CLGTr64eq.Fragment)), 0xb)>;
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def CLGEv2i64compare:
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CodeFrag<(CEQIv4i32 (GBv4i32 (ORv4i32 CLGTv2i64ugt.Fragment,
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CLGTv2i64eq.Fragment)), 0xf)>;
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multiclass CompareLogicalGreaterEqual64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(ORi32_v4i32 CLGEr64compare.Fragment)>;
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def v2i64: CodeFrag<CLGEv2i64compare.Fragment>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGEr64compare.Fragment))>;
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def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGEv2i64compare.Fragment))>;
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}
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defm I64LGE: CompareLogicalGreaterEqual64;
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def : Pat<(setuge R64C:$rA, R64C:$rB), I64LGEr64.Fragment>;
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def : Pat<(setuge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
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I64LGEv2i64.Fragment>;
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// i64 setult:
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def : I64SETCCNegCond<setult, I64LGEr64>;
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def : I64SELECTNegCond<setult, I64LGEr64>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// i64 setgt/setle:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def CGTr64sgt:
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CodeFrag<(CGTv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>;
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def CGTr64eq:
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CodeFrag<(CEQv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>;
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def CGTr64compare:
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CodeFrag<(SELBv2i64 CGTr64sgt.Fragment,
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(XSWDv2i64 CGTr64sgt.Fragment),
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CGTr64eq.Fragment)>;
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def CGTv2i64sgt:
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CodeFrag<(CGTv4i32 VECREG:$rA, VECREG:$rB)>;
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def CGTv2i64eq:
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CodeFrag<(CEQv4i32 VECREG:$rA, VECREG:$rB)>;
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def CGTv2i64compare:
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CodeFrag<(SELBv2i64 CGTv2i64sgt.Fragment,
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(XSWDv2i64 CGTr64sgt.Fragment),
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CGTv2i64eq.Fragment)>;
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multiclass CompareGreaterThan64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(ORi32_v4i32 CGTr64compare.Fragment)>;
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def v2i64: CodeFrag<CGTv2i64compare.Fragment>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CGTr64compare.Fragment))>;
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def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CGTv2i64compare.Fragment))>;
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}
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defm I64GT: CompareLogicalGreaterThan64;
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def : Pat<(setgt R64C:$rA, R64C:$rB), I64GTr64.Fragment>;
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def : Pat<(setgt (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
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I64GTv2i64.Fragment>;
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// i64 setult:
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def : I64SETCCNegCond<setle, I64GTr64>;
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def : I64SELECTNegCond<setle, I64GTr64>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// i64 setge/setlt:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def CGEr64compare:
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CodeFrag<(CGTIv4i32 (GBv4i32 (ORv4i32 CGTr64sgt.Fragment,
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CGTr64eq.Fragment)), 0xb)>;
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def CGEv2i64compare:
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CodeFrag<(CEQIv4i32 (GBv4i32 (ORv4i32 CGTv2i64sgt.Fragment,
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CGTv2i64eq.Fragment)), 0xf)>;
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multiclass CompareGreaterEqual64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(ORi32_v4i32 CGEr64compare.Fragment)>;
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def v2i64: CodeFrag<CGEv2i64compare.Fragment>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CGEr64compare.Fragment))>;
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def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CGEv2i64compare.Fragment))>;
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}
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defm I64GE: CompareGreaterEqual64;
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def : Pat<(setge R64C:$rA, R64C:$rB), I64GEr64.Fragment>;
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def : Pat<(setge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
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I64GEv2i64.Fragment>;
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// i64 setult:
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def : I64SETCCNegCond<setlt, I64GEr64>;
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def : I64SELECTNegCond<setlt, I64GEr64>;
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