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https://github.com/c64scene-ar/llvm-6502.git
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3986785046
We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
3.2 KiB
LLVM
77 lines
3.2 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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;RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
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;EG-CHECK: @test_select_v2i32
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: @test_select_v2i32
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;SI-CHECK: V_CNDMASK_B32_e64
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;SI-CHECK: V_CNDMASK_B32_e64
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define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
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entry:
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%0 = load <2 x i32> addrspace(1)* %in0
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%1 = load <2 x i32> addrspace(1)* %in1
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%cmp = icmp ne <2 x i32> %0, %1
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%result = select <2 x i1> %cmp, <2 x i32> %0, <2 x i32> %1
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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;EG-CHECK: @test_select_v2f32
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: @test_select_v2f32
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;SI-CHECK: V_CNDMASK_B32_e64
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;SI-CHECK: V_CNDMASK_B32_e64
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define void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) {
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entry:
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%0 = load <2 x float> addrspace(1)* %in0
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%1 = load <2 x float> addrspace(1)* %in1
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%cmp = fcmp une <2 x float> %0, %1
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%result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1
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store <2 x float> %result, <2 x float> addrspace(1)* %out
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ret void
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}
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;EG-CHECK: @test_select_v4i32
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: @test_select_v4i32
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;SI-CHECK: V_CNDMASK_B32_e64
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;SI-CHECK: V_CNDMASK_B32_e64
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;SI-CHECK: V_CNDMASK_B32_e64
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;SI-CHECK: V_CNDMASK_B32_e64
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define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
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entry:
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%0 = load <4 x i32> addrspace(1)* %in0
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%1 = load <4 x i32> addrspace(1)* %in1
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%cmp = icmp ne <4 x i32> %0, %1
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%result = select <4 x i1> %cmp, <4 x i32> %0, <4 x i32> %1
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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;EG-CHECK: @test_select_v4f32
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) {
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entry:
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%0 = load <4 x float> addrspace(1)* %in0
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%1 = load <4 x float> addrspace(1)* %in1
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%cmp = fcmp une <4 x float> %0, %1
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%result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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