Tilmann Scheller 9bd0d2a6a0 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRH/LDRSH instructions. ...

The ARM ARM prohibits LDRH/LDRSH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214499 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-01 11:33:47 +00:00

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Analysis

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Assembler

verify-uselistorder: Change the default -num-shuffles=5

2014-07-31 18:46:24 +00:00

Bindings

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Bitcode

verify-uselistorder: Change the default -num-shuffles=5

2014-07-31 18:46:24 +00:00

BugPoint

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CodeGen

[mips][PR19612] Fix va_arg for big-endian mode.

2014-08-01 09:17:39 +00:00

DebugInfo

Use "weak alias" instead of "alias weak"

2014-07-30 22:51:54 +00:00

ExecutionEngine

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Feature

Use "weak alias" instead of "alias weak"

2014-07-30 22:51:54 +00:00

FileCheck

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Instrumentation

[msan] Fix handling of array types.

2014-07-31 11:02:27 +00:00

Integer

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JitListener

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Linker

Use "weak alias" instead of "alias weak"

2014-07-30 22:51:54 +00:00

LTO

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MC

[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRH/LDRSH instructions.

2014-08-01 11:33:47 +00:00

Object

Use "weak alias" instead of "alias weak"

2014-07-30 22:51:54 +00:00

Other

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TableGen

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tools

llvm-profdata: Add a test for mismatched numbers of counters

2014-07-30 23:36:06 +00:00

Transforms

SLPVectorizer: improved scheduling algorithm.

2014-08-01 09:20:42 +00:00

Unit

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Verifier

Use "weak alias" instead of "alias weak"

2014-07-30 22:51:54 +00:00

YAMLParser

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.clang-format

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CMakeLists.txt

Rename llvm-uselistorder => verify-uselistorder

2014-07-30 17:11:27 +00:00

lit.cfg

Rename llvm-uselistorder => verify-uselistorder

2014-07-30 17:11:27 +00:00

lit.site.cfg.in

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Makefile

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Makefile.tests

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TestRunner.sh

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