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llvm-6502/test/CodeGen/X86/vec_set-F.ll
Evan Cheng d880b97257 Handle a few more cases of folding load i64 into xmm and zero top bits.
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09 21:53:03 +00:00

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LLVM

; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movq
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep mov | count 3
define <2 x i64> @t1(<2 x i64>* %ptr) nounwind {
%tmp45 = bitcast <2 x i64>* %ptr to <2 x i32>*
%tmp615 = load <2 x i32>* %tmp45
%tmp7 = bitcast <2 x i32> %tmp615 to i64
%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %tmp7, i32 0
ret <2 x i64> %tmp8
}
define <2 x i64> @t2(i64 %x) nounwind {
%tmp717 = bitcast i64 %x to double
%tmp8 = insertelement <2 x double> undef, double %tmp717, i32 0
%tmp9 = insertelement <2 x double> %tmp8, double 0.000000e+00, i32 1
%tmp11 = bitcast <2 x double> %tmp9 to <2 x i64>
ret <2 x i64> %tmp11
}