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https://github.com/c64scene-ar/llvm-6502.git
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e4b2165648
The PPCTargetLowering::SelectAddressRegImm routine needs to handle FrameIndex nodes in a special manner, by tranlating them into a TargetFrameIndex node. This was done in most cases, but seems to have been neglected in one path: when the input tree has an OR of the FrameIndex with an immediate. This can happen if the FrameIndex can be proven to be sufficiently aligned that an OR of that immediate is equivalent to an ADD. The missing handling of FrameIndex in that case caused the SelectionDAG instruction selection to miss opportunities to merge the OR back into the FrameIndex node, leading to superfluous addi/ori instructions in the final assembler output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213482 91177308-0d34-0410-b5e6-96231b3b80d8
182 lines
5.9 KiB
LLVM
182 lines
5.9 KiB
LLVM
; RUN: llc -O0 -mcpu=ppc64 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
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; RUN: llc -O0 -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s
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; RUN: llc -O0 -mcpu=ppc970 -mtriple=powerpc64-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN64 %s
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; Test case for PR 14779: anonymous aggregates are not handled correctly.
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; Darwin bug report PR 15821 is similar.
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; The bug is triggered by passing a byval structure after an anonymous
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; aggregate.
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%tarray = type { i64, i8* }
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define i8* @func1({ i64, i8* } %array, i8* %ptr) {
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entry:
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%array_ptr = extractvalue {i64, i8* } %array, 1
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%cond = icmp eq i8* %array_ptr, %ptr
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br i1 %cond, label %equal, label %unequal
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equal:
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ret i8* %array_ptr
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unequal:
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ret i8* %ptr
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}
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; CHECK-LABEL: func1:
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; CHECK: cmpld {{[0-9]+}}, 4, 5
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; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
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; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
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; CHECK: ld 3, -[[OFFSET1]](1)
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; CHECK: ld 3, -[[OFFSET2]](1)
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; DARWIN32: _func1:
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; DARWIN32: mr
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; DARWIN32: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
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; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
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; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REGB]]
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; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]]
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; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
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; DARWIN32: lwz r3, -[[OFFSET1]]
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; DARWIN32: lwz r3, -[[OFFSET2]]
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; DARWIN64: _func1:
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; DARWIN64: mr
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; DARWIN64: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
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; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
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; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REGB]]
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; DARWIN64: std r[[REG1]], -[[OFFSET1:[0-9]+]]
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; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
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; DARWIN64: ld r3, -[[OFFSET1]]
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; DARWIN64: ld r3, -[[OFFSET2]]
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define i8* @func2({ i64, i8* } %array1, %tarray* byval %array2) {
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entry:
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%array1_ptr = extractvalue {i64, i8* } %array1, 1
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%tmp = getelementptr inbounds %tarray* %array2, i32 0, i32 1
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%array2_ptr = load i8** %tmp
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%cond = icmp eq i8* %array1_ptr, %array2_ptr
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br i1 %cond, label %equal, label %unequal
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equal:
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ret i8* %array1_ptr
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unequal:
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ret i8* %array2_ptr
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}
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; CHECK-LABEL: func2:
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; CHECK: ld [[REG2:[0-9]+]], 72(1)
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; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
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; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
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; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]
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; CHECK: ld 3, -[[OFFSET2]](1)
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; CHECK: ld 3, -[[OFFSET1]](1)
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; DARWIN32: _func2:
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; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36
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; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
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; DARWIN32: mr
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; DARWIN32: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
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; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REG2]]
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; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
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; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
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; DARWIN32: lwz r3, -[[OFFSET1]]
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; DARWIN32: lwz r3, -[[OFFSET2]]
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; DARWIN64: _func2:
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; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1)
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; DARWIN64: mr
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; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
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; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REG2]]
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; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
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; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
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; DARWIN64: ld r3, -[[OFFSET1]]
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; DARWIN64: ld r3, -[[OFFSET2]]
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define i8* @func3({ i64, i8* }* byval %array1, %tarray* byval %array2) {
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entry:
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%tmp1 = getelementptr inbounds { i64, i8* }* %array1, i32 0, i32 1
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%array1_ptr = load i8** %tmp1
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%tmp2 = getelementptr inbounds %tarray* %array2, i32 0, i32 1
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%array2_ptr = load i8** %tmp2
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%cond = icmp eq i8* %array1_ptr, %array2_ptr
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br i1 %cond, label %equal, label %unequal
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equal:
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ret i8* %array1_ptr
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unequal:
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ret i8* %array2_ptr
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}
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; CHECK-LABEL: func3:
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; CHECK: ld [[REG3:[0-9]+]], 72(1)
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; CHECK: ld [[REG4:[0-9]+]], 56(1)
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; CHECK: cmpld {{[0-9]+}}, [[REG4]], [[REG3]]
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; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1)
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; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1)
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; CHECK: ld 3, -[[OFFSET2]](1)
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; CHECK: ld 3, -[[OFFSET1]](1)
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; DARWIN32: _func3:
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; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36
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; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24
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; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]])
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; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]])
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; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
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; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
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; DARWIN32: stw r[[REG4]], -[[OFFSET2:[0-9]+]]
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; DARWIN32: lwz r3, -[[OFFSET2]]
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; DARWIN32: lwz r3, -[[OFFSET1]]
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; DARWIN64: _func3:
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; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1)
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; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1)
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; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
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; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
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; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]]
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; DARWIN64: ld r3, -[[OFFSET2]]
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; DARWIN64: ld r3, -[[OFFSET1]]
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define i8* @func4(i64 %p1, i64 %p2, i64 %p3, i64 %p4,
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i64 %p5, i64 %p6, i64 %p7, i64 %p8,
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{ i64, i8* } %array1, %tarray* byval %array2) {
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entry:
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%array1_ptr = extractvalue {i64, i8* } %array1, 1
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%tmp = getelementptr inbounds %tarray* %array2, i32 0, i32 1
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%array2_ptr = load i8** %tmp
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%cond = icmp eq i8* %array1_ptr, %array2_ptr
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br i1 %cond, label %equal, label %unequal
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equal:
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ret i8* %array1_ptr
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unequal:
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ret i8* %array2_ptr
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}
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; CHECK-LABEL: func4:
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; CHECK: ld [[REG3:[0-9]+]], 136(1)
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; CHECK: ld [[REG2:[0-9]+]], 120(1)
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; CHECK: cmpld {{[0-9]+}}, [[REG2]], [[REG3]]
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; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1)
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; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1)
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; CHECK: ld 3, -[[OFFSET1]](1)
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; CHECK: ld 3, -[[OFFSET2]](1)
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; DARWIN32: _func4:
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; DARWIN32: lwz r[[REG4:[0-9]+]], 96(r1)
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; DARWIN32: addi r[[REG1:[0-9]+]], r1, 100
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; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1)
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; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]]
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; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
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; DARWIN32: stw r[[REG4]], -[[OFFSET1:[0-9]+]]
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; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]]
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; DARWIN32: lwz r[[REG1]], -[[OFFSET1]]
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; DARWIN32: lwz r[[REG1]], -[[OFFSET2]]
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; DARWIN64: _func4:
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; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1)
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; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1)
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; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]]
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; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG2]], r[[REG3]]
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; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]]
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; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]]
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; DARWIN64: ld r3, -[[OFFSET1]]
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; DARWIN64: ld r3, -[[OFFSET2]]
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