llvm-6502/test/CodeGen/NVPTX/sched2.ll
Justin Holewinski d73dc544f5 Propagate DAG node ordering during type legalization and instruction selection
A node's ordering is only propagated during legalization if (a) the new node does
not have an ordering (is not a CSE'd node), or (b) the new node has an ordering
that is higher than the node being legalized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 00:10:32 +00:00

33 lines
796 B
LLVM

; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
define void @foo(<2 x i32>* %a) {
; CHECK: .func foo
; CHECK: ld.v2.u32
; CHECK-NEXT: ld.v2.u32
; CHECK-NEXT: ld.v2.u32
; CHECK-NEXT: ld.v2.u32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
%ptr0 = getelementptr <2 x i32>* %a, i32 0
%val0 = load <2 x i32>* %ptr0
%ptr1 = getelementptr <2 x i32>* %a, i32 1
%val1 = load <2 x i32>* %ptr1
%ptr2 = getelementptr <2 x i32>* %a, i32 2
%val2 = load <2 x i32>* %ptr2
%ptr3 = getelementptr <2 x i32>* %a, i32 3
%val3 = load <2 x i32>* %ptr3
%t0 = add <2 x i32> %val0, %val1
%t1 = add <2 x i32> %t0, %val2
%t2 = add <2 x i32> %t1, %val3
store <2 x i32> %t2, <2 x i32>* %a
ret void
}