mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 16:29:20 +00:00
29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
290 lines
6.9 KiB
LLVM
290 lines
6.9 KiB
LLVM
; RUN: llc < %s -mcpu=cyclone -verify-machineinstrs -aarch64-ccmp -aarch64-stress-ccmp | FileCheck %s
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target triple = "arm64-apple-ios"
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; CHECK: single_same
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; CHECK: cmp w0, #5
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; CHECK-NEXT: ccmp w1, #17, #4, ne
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; CHECK-NEXT: b.ne
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; CHECK: %if.then
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; CHECK: bl _foo
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; CHECK: %if.end
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define i32 @single_same(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 5
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%cmp1 = icmp eq i32 %b, 17
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Different condition codes for the two compares.
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; CHECK: single_different
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; CHECK: cmp w0, #6
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; CHECK-NEXT: ccmp w1, #17, #0, ge
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; CHECK-NEXT: b.eq
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; CHECK: %if.then
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; CHECK: bl _foo
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; CHECK: %if.end
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define i32 @single_different(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp sle i32 %a, 5
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%cmp1 = icmp ne i32 %b, 17
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Second block clobbers the flags, can't convert (easily).
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; CHECK: single_flagclobber
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; CHECK: cmp
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; CHECK: b.eq
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; CHECK: cmp
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; CHECK: b.gt
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define i32 @single_flagclobber(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 5
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br i1 %cmp, label %if.then, label %lor.lhs.false
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lor.lhs.false: ; preds = %entry
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%cmp1 = icmp slt i32 %b, 7
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%mul = shl nsw i32 %b, 1
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%add = add nsw i32 %b, 1
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%cond = select i1 %cmp1, i32 %mul, i32 %add
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%cmp2 = icmp slt i32 %cond, 17
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br i1 %cmp2, label %if.then, label %if.end
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if.then: ; preds = %lor.lhs.false, %entry
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end: ; preds = %if.then, %lor.lhs.false
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ret i32 7
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}
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; Second block clobbers the flags and ends with a tbz terminator.
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; CHECK: single_flagclobber_tbz
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; CHECK: cmp
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; CHECK: b.eq
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; CHECK: cmp
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; CHECK: tbz
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define i32 @single_flagclobber_tbz(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 5
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br i1 %cmp, label %if.then, label %lor.lhs.false
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lor.lhs.false: ; preds = %entry
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%cmp1 = icmp slt i32 %b, 7
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%mul = shl nsw i32 %b, 1
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%add = add nsw i32 %b, 1
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%cond = select i1 %cmp1, i32 %mul, i32 %add
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%and = and i32 %cond, 8
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%cmp2 = icmp ne i32 %and, 0
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br i1 %cmp2, label %if.then, label %if.end
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if.then: ; preds = %lor.lhs.false, %entry
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end: ; preds = %if.then, %lor.lhs.false
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ret i32 7
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}
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; Speculatively execute division by zero.
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; The sdiv/udiv instructions do not trap when the divisor is zero, so they are
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; safe to speculate.
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; CHECK: speculate_division
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; CHECK-NOT: cmp
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; CHECK: sdiv
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; CHECK: cmp
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; CHECK-NEXT: ccmp
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define i32 @speculate_division(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %land.lhs.true, label %if.end
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land.lhs.true:
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%div = sdiv i32 %b, %a
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%cmp1 = icmp slt i32 %div, 17
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br i1 %cmp1, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Floating point compare.
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; CHECK: single_fcmp
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; CHECK: cmp
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; CHECK-NOT: b.
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; CHECK: fccmp {{.*}}, #8, ge
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; CHECK: b.lt
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define i32 @single_fcmp(i32 %a, float %b) nounwind ssp {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %land.lhs.true, label %if.end
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land.lhs.true:
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%conv = sitofp i32 %a to float
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%div = fdiv float %b, %conv
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%cmp1 = fcmp oge float %div, 1.700000e+01
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br i1 %cmp1, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Chain multiple compares.
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; CHECK: multi_different
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; CHECK: cmp
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; CHECK: ccmp
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; CHECK: ccmp
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; CHECK: b.
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define void @multi_different(i32 %a, i32 %b, i32 %c) nounwind ssp {
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entry:
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%cmp = icmp sgt i32 %a, %b
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br i1 %cmp, label %land.lhs.true, label %if.end
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land.lhs.true:
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%div = sdiv i32 %b, %a
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%cmp1 = icmp eq i32 %div, 5
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%cmp4 = icmp sgt i32 %div, %c
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%or.cond = and i1 %cmp1, %cmp4
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret void
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}
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; Convert a cbz in the head block.
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; CHECK: cbz_head
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; CHECK: cmp w0, #0
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; CHECK: ccmp
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define i32 @cbz_head(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp ne i32 %b, 17
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Check that the immediate operand is in range. The ccmp instruction encodes a
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; smaller range of immediates than subs/adds.
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; The ccmp immediates must be in the range 0-31.
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; CHECK: immediate_range
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; CHECK-NOT: ccmp
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define i32 @immediate_range(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 5
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%cmp1 = icmp eq i32 %b, 32
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Convert a cbz in the second block.
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; CHECK: cbz_second
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; CHECK: cmp w0, #0
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; CHECK: ccmp w1, #0, #0, ne
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; CHECK: b.eq
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define i32 @cbz_second(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp ne i32 %b, 0
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Convert a cbnz in the second block.
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; CHECK: cbnz_second
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; CHECK: cmp w0, #0
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; CHECK: ccmp w1, #0, #4, ne
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; CHECK: b.ne
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define i32 @cbnz_second(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp eq i32 %b, 0
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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declare i32 @foo()
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%str1 = type { %str2 }
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%str2 = type { [24 x i8], i8*, i32, %str1*, i32, [4 x i8], %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, i8*, i8, i8*, %str1*, i8* }
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; Test case distilled from 126.gcc.
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; The phi in sw.bb.i.i gets multiple operands for the %entry predecessor.
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; CHECK: build_modify_expr
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define void @build_modify_expr() nounwind ssp {
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entry:
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switch i32 undef, label %sw.bb.i.i [
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i32 69, label %if.end85
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i32 70, label %if.end85
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i32 71, label %if.end85
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i32 72, label %if.end85
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i32 73, label %if.end85
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i32 105, label %if.end85
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i32 106, label %if.end85
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]
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if.end85:
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ret void
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sw.bb.i.i:
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%ref.tr.i.i = phi %str1* [ %0, %sw.bb.i.i ], [ undef, %entry ]
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%operands.i.i = getelementptr inbounds %str1* %ref.tr.i.i, i64 0, i32 0, i32 2
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%arrayidx.i.i = bitcast i32* %operands.i.i to %str1**
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%0 = load %str1** %arrayidx.i.i, align 8
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%code1.i.i.phi.trans.insert = getelementptr inbounds %str1* %0, i64 0, i32 0, i32 0, i64 16
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br label %sw.bb.i.i
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}
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