mirror of
https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
2.4 KiB
LLVM
76 lines
2.4 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
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define void @bar(<8 x i16> %arg, <8 x i8>* %p) nounwind {
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; CHECK-LABEL: bar:
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; CHECK: xtn.8b v[[REG:[0-9]+]], v0
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; CHECK-NEXT: str d[[REG]], [x0]
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; CHECK-NEXT: ret
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%tmp = trunc <8 x i16> %arg to <8 x i8>
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store <8 x i8> %tmp, <8 x i8>* %p, align 8
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ret void
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}
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@zptr8 = common global i8* null, align 8
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@zptr16 = common global i16* null, align 8
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@zptr32 = common global i32* null, align 8
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define void @fct32(i32 %arg, i64 %var) {
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; CHECK: fct32
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; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr32@GOTPAGE
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; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr32@GOTPAGEOFF]
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; CHECK: ldr [[GLOBALADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
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; w0 is %arg
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; CHECK-NEXT: sub w[[OFFSETREGNUM:[0-9]+]], w0, #1
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; w1 is %var truncated
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; CHECK-NEXT: str w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #2]
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; CHECK-NEXT: ret
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bb:
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%.pre37 = load i32** @zptr32, align 8
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%dec = add nsw i32 %arg, -1
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%idxprom8 = sext i32 %dec to i64
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%arrayidx9 = getelementptr inbounds i32* %.pre37, i64 %idxprom8
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%tmp = trunc i64 %var to i32
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store i32 %tmp, i32* %arrayidx9, align 4
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ret void
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}
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define void @fct16(i32 %arg, i64 %var) {
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; CHECK: fct16
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; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr16@GOTPAGE
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; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr16@GOTPAGEOFF]
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; CHECK: ldr [[GLOBALADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
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; w0 is %arg
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; CHECK-NEXT: sub w[[OFFSETREGNUM:[0-9]+]], w0, #1
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; w1 is %var truncated
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; CHECK-NEXT: strh w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #1]
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; CHECK-NEXT: ret
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bb:
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%.pre37 = load i16** @zptr16, align 8
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%dec = add nsw i32 %arg, -1
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%idxprom8 = sext i32 %dec to i64
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%arrayidx9 = getelementptr inbounds i16* %.pre37, i64 %idxprom8
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%tmp = trunc i64 %var to i16
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store i16 %tmp, i16* %arrayidx9, align 4
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ret void
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}
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define void @fct8(i32 %arg, i64 %var) {
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; CHECK: fct8
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; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr8@GOTPAGE
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; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr8@GOTPAGEOFF]
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; CHECK: ldr [[BASEADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
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; w0 is %arg
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; CHECK-NEXT: add [[ADDR:x[0-9]+]], [[BASEADDR]], w0, sxtw
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; w1 is %var truncated
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; CHECK-NEXT: sturb w1, {{\[}}[[ADDR]], #-1]
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; CHECK-NEXT: ret
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bb:
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%.pre37 = load i8** @zptr8, align 8
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%dec = add nsw i32 %arg, -1
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%idxprom8 = sext i32 %dec to i64
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%arrayidx9 = getelementptr inbounds i8* %.pre37, i64 %idxprom8
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%tmp = trunc i64 %var to i8
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store i8 %tmp, i8* %arrayidx9, align 4
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ret void
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}
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