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9caa5bdec0
llvm-6502/test/CodeGen
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Peter Collingbourne 9caa5bdec0 CodeGen: do not attempt to invalidate virtual registers for zero-sized phis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224615 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-19 20:50:07 +00:00
..
AArch64 IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
ARM Add a new string member to the TargetOptions struct for the name 2014-12-18 02:20:58 +00:00
CPP
Generic CodeGen: do not attempt to invalidate virtual registers for zero-sized phis. 2014-12-19 20:50:07 +00:00
Hexagon IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Inputs IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Mips [mips][microMIPS] Fix bugs related to atomic SC/LL instructions 2014-12-18 16:39:29 +00:00
MSP430 Drop the W postfix on the 16-bit registers. 2014-09-10 06:58:14 +00:00
NVPTX [NVPTX] Fix bugs related to isSingleValueType 2014-12-17 17:59:04 +00:00
PowerPC [PowerPC] Improve instruction selection bit-permuting operations (32-bit) 2014-12-16 05:51:41 +00:00
R600 R600/SI: Fix f64 inline immediates 2014-12-17 21:04:08 +00:00
SPARC IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
SystemZ IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Thumb IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Thumb2 IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
X86 merge consecutive stores of extracted vector elements 2014-12-19 20:23:41 +00:00
XCore IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00