llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-04 22:07:27 +00:00

History

Duncan Sands 28b77e968d Add codegen support for vector select (in the IR this means a select with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8		2011-09-06 19:07:46 +00:00
..
MCTargetDesc	Move TargetRegistry and TargetSelect from Target to Support where they belong.	2011-08-24 18:08:43 +00:00
TargetInfo	Move TargetRegistry and TargetSelect from Target to Support where they belong.	2011-08-24 18:08:43 +00:00
Alpha.h	Next round of MC refactoring. This patch factor MC table instantiations, MC	2011-07-14 20:59:42 +00:00
Alpha.td
AlphaAsmPrinter.cpp	Move TargetRegistry and TargetSelect from Target to Support where they belong.	2011-08-24 18:08:43 +00:00
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaFrameLowering.cpp
AlphaFrameLowering.h
AlphaInstrFormats.td
AlphaInstrInfo.cpp	Move TargetRegistry and TargetSelect from Target to Support where they belong.	2011-08-24 18:08:43 +00:00
AlphaInstrInfo.h
AlphaInstrInfo.td	Code generation for 'fence' instruction.	2011-07-27 22:21:52 +00:00
AlphaISelDAGToDAG.cpp
AlphaISelLowering.cpp	Add codegen support for vector select (in the IR this means a select	2011-09-06 19:07:46 +00:00
AlphaISelLowering.h	Add codegen support for vector select (in the IR this means a select	2011-09-06 19:07:46 +00:00
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaRegisterInfo.cpp	Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for	2011-07-18 22:29:13 +00:00
AlphaRegisterInfo.h	Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down	2011-07-18 20:57:22 +00:00
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSelectionDAGInfo.cpp
AlphaSelectionDAGInfo.h
AlphaSubtarget.cpp	Move TargetRegistry and TargetSelect from Target to Support where they belong.	2011-08-24 18:08:43 +00:00
AlphaSubtarget.h
AlphaTargetMachine.cpp	Move TargetRegistry and TargetSelect from Target to Support where they belong.	2011-08-24 18:08:43 +00:00
AlphaTargetMachine.h	- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.	2011-07-20 07:51:56 +00:00
CMakeLists.txt	Rewrite the CMake build to use explicit dependencies between libraries,	2011-07-29 00:14:25 +00:00
Makefile	Next round of MC refactoring. This patch factor MC table instantiations, MC	2011-07-14 20:59:42 +00:00
README.txt

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum across bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extensions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html