mirror of
https://github.com/c64scene-ar/llvm-6502.git
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84a2c2bbb5
This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175205 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
2.7 KiB
TableGen
70 lines
2.7 KiB
TableGen
//===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Functional Units
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def LSUNIT : FuncUnit; // SLOT0
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def LUNIT : FuncUnit; // SLOT1
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def MUNIT : FuncUnit; // SLOT2
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def SUNIT : FuncUnit; // SLOT3
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def LOOPUNIT : FuncUnit;
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// Itinerary classes
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def ALU32 : InstrItinClass;
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def ALU64 : InstrItinClass;
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def CR : InstrItinClass;
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def J : InstrItinClass;
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def JR : InstrItinClass;
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def LD : InstrItinClass;
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def LD0 : InstrItinClass;
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def M : InstrItinClass;
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def ST : InstrItinClass;
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def ST0 : InstrItinClass;
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def S : InstrItinClass;
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def SYS : InstrItinClass;
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def ENDLOOP : InstrItinClass;
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def PSEUDO : InstrItinClass;
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def PSEUDOM : InstrItinClass;
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def HexagonItineraries :
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ProcessorItineraries<[LSUNIT, LUNIT, MUNIT, SUNIT, LOOPUNIT], [], [
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InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
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InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,
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InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,
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InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,
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InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,
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InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,
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InstrItinData<LD0 , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,
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InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<ST0 , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,
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InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<ENDLOOP, [InstrStage<1, [LOOPUNIT]>]>,
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InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
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InstrItinData<PSEUDOM, [InstrStage<1, [MUNIT, SUNIT], 0>,
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InstrStage<1, [MUNIT, SUNIT]>]>
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]>;
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def HexagonModel : SchedMachineModel {
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// Max issue per cycle == bundle width.
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let IssueWidth = 4;
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let Itineraries = HexagonItineraries;
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let LoadLatency = 1;
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}
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//===----------------------------------------------------------------------===//
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// V4 Machine Info +
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//===----------------------------------------------------------------------===//
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include "HexagonScheduleV4.td"
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//===----------------------------------------------------------------------===//
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// V4 Machine Info -
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//===----------------------------------------------------------------------===//
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