mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-12 00:29:20 +00:00
859df5e9f9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8
446 lines
13 KiB
C++
446 lines
13 KiB
C++
//===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "thumb2-it"
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#include "ARM.h"
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#include "ARMMachineFunctionInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumITs, "Number of IT blocks inserted");
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STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
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namespace {
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class Thumb2ITBlockPass : public MachineFunctionPass {
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bool PreRegAlloc;
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public:
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static char ID;
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Thumb2ITBlockPass(bool PreRA) :
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MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
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const Thumb2InstrInfo *TII;
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const TargetRegisterInfo *TRI;
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ARMFunctionInfo *AFI;
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "Thumb IT blocks insertion pass";
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}
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private:
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bool MoveCPSRUseUp(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator E,
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unsigned PredReg,
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ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
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bool &Done);
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void FindITBlockRanges(MachineBasicBlock &MBB,
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SmallVector<MachineInstr*,4> &FirstUses,
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SmallVector<MachineInstr*,4> &LastUses);
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bool InsertITBlock(MachineInstr *First, MachineInstr *Last);
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bool InsertITBlocks(MachineBasicBlock &MBB);
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bool MoveCopyOutOfITBlock(MachineInstr *MI,
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ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
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SmallSet<unsigned, 4> &Defs,
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SmallSet<unsigned, 4> &Uses);
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bool InsertITInstructions(MachineBasicBlock &MBB);
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};
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char Thumb2ITBlockPass::ID = 0;
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}
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static ARMCC::CondCodes getPredicate(const MachineInstr *MI, unsigned &PredReg){
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unsigned Opc = MI->getOpcode();
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if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
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return ARMCC::AL;
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return llvm::getInstrPredicate(MI, PredReg);
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}
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bool
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Thumb2ITBlockPass::MoveCPSRUseUp(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator E,
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unsigned PredReg,
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ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
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bool &Done) {
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SmallSet<unsigned, 4> Defs, Uses;
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MachineBasicBlock::iterator I = MBBI;
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// Look for next CPSR use by scanning up to 4 instructions.
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for (unsigned i = 0; i < 4; ++i) {
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MachineInstr *MI = &*I;
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unsigned MPredReg = 0;
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ARMCC::CondCodes MCC = getPredicate(MI, MPredReg);
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if (MCC != ARMCC::AL) {
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if (MPredReg != PredReg || (MCC != CC && MCC != OCC))
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return false;
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// Check if the instruction is using any register that's defined
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// below the previous predicated instruction. Also return false if
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// it defines any register which is used in between.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (MO.isDef()) {
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if (Reg == PredReg || Uses.count(Reg))
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return false;
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} else {
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if (Defs.count(Reg))
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return false;
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}
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}
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Done = (I == E);
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MBB.remove(MI);
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MBB.insert(MBBI, MI);
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++NumMovedInsts;
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return true;
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}
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (MO.isDef()) {
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if (Reg == PredReg)
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return false;
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Defs.insert(Reg);
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} else
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Uses.insert(Reg);
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}
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if (I == E)
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break;
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++I;
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}
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return false;
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}
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static bool isCPSRLiveout(MachineBasicBlock &MBB) {
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for (MachineBasicBlock::succ_iterator I = MBB.succ_begin(),
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E = MBB.succ_end(); I != E; ++I) {
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if ((*I)->isLiveIn(ARM::CPSR))
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return true;
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}
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return false;
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}
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void Thumb2ITBlockPass::FindITBlockRanges(MachineBasicBlock &MBB,
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SmallVector<MachineInstr*,4> &FirstUses,
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SmallVector<MachineInstr*,4> &LastUses) {
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bool SeenUse = false;
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MachineOperand *LastDef = 0;
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MachineOperand *LastUse = 0;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineInstr *MI = &*MBBI;
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++MBBI;
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MachineOperand *Def = 0;
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MachineOperand *Use = 0;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.getReg() != ARM::CPSR)
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continue;
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if (MO.isDef()) {
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assert(Def == 0 && "Multiple defs of CPSR?");
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Def = &MO;
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} else {
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assert(Use == 0 && "Multiple uses of CPSR?");
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Use = &MO;
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}
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}
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if (Use) {
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LastUse = Use;
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if (!SeenUse) {
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FirstUses.push_back(MI);
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SeenUse = true;
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}
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}
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if (Def) {
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if (LastUse) {
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LastUses.push_back(LastUse->getParent());
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LastUse = 0;
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}
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LastDef = Def;
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SeenUse = false;
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}
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}
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if (LastUse) {
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// Is the last use a kill?
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if (isCPSRLiveout(MBB))
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LastUses.push_back(0);
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else
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LastUses.push_back(LastUse->getParent());
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}
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}
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bool Thumb2ITBlockPass::InsertITBlock(MachineInstr *First, MachineInstr *Last) {
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if (First == Last)
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return false;
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bool Modified = false;
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MachineBasicBlock *MBB = First->getParent();
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MachineBasicBlock::iterator MBBI = First;
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MachineBasicBlock::iterator E = Last;
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if (First->getDesc().isBranch() || First->getDesc().isReturn())
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return false;
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unsigned PredReg = 0;
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ARMCC::CondCodes CC = getPredicate(First, PredReg);
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if (CC == ARMCC::AL)
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return Modified;
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// Move uses of the CPSR together if possible.
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ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
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do {
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++MBBI;
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if (MBBI->getDesc().isBranch() || MBBI->getDesc().isReturn())
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return Modified;
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MachineInstr *NMI = &*MBBI;
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unsigned NPredReg = 0;
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ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
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if (NCC != CC && NCC != OCC) {
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if (NCC != ARMCC::AL)
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return Modified;
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assert(MBBI != E);
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bool Done = false;
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if (!MoveCPSRUseUp(*MBB, MBBI, E, PredReg, CC, OCC, Done))
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return Modified;
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Modified = true;
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if (Done)
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MBBI = E;
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}
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} while (MBBI != E);
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return true;
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}
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bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
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SmallVector<MachineInstr*, 4> FirstUses;
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SmallVector<MachineInstr*, 4> LastUses;
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FindITBlockRanges(MBB, FirstUses, LastUses);
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assert(FirstUses.size() == LastUses.size() && "Incorrect range information!");
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bool Modified = false;
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for (unsigned i = 0, e = FirstUses.size(); i != e; ++i) {
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if (LastUses[i] == 0)
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// Must be the last pair where CPSR is live out of the block.
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return Modified;
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Modified |= InsertITBlock(FirstUses[i], LastUses[i]);
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}
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return Modified;
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}
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/// TrackDefUses - Tracking what registers are being defined and used by
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/// instructions in the IT block. This also tracks "dependencies", i.e. uses
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/// in the IT block that are defined before the IT instruction.
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static void TrackDefUses(MachineInstr *MI,
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SmallSet<unsigned, 4> &Defs,
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SmallSet<unsigned, 4> &Uses,
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const TargetRegisterInfo *TRI) {
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SmallVector<unsigned, 4> LocalDefs;
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SmallVector<unsigned, 4> LocalUses;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
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continue;
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if (MO.isUse())
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LocalUses.push_back(Reg);
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else
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LocalDefs.push_back(Reg);
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}
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for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
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unsigned Reg = LocalUses[i];
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Uses.insert(Reg);
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg)
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Uses.insert(*Subreg);
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}
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for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
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unsigned Reg = LocalDefs[i];
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Defs.insert(Reg);
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg)
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Defs.insert(*Subreg);
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if (Reg == ARM::CPSR)
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continue;
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}
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}
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bool
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Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
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ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
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SmallSet<unsigned, 4> &Defs,
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SmallSet<unsigned, 4> &Uses) {
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
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assert(SrcSubIdx == 0 && DstSubIdx == 0 &&
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"Sub-register indices still around?");
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// llvm models select's as two-address instructions. That means a copy
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// is inserted before a t2MOVccr, etc. If the copy is scheduled in
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// between selects we would end up creating multiple IT blocks.
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// First check if it's safe to move it.
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if (Uses.count(DstReg) || Defs.count(SrcReg))
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return false;
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// Then peek at the next instruction to see if it's predicated on CC or OCC.
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// If not, then there is nothing to be gained by moving the copy.
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MachineBasicBlock::iterator I = MI; ++I;
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MachineBasicBlock::iterator E = MI->getParent()->end();
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if (I != E) {
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while (I != E && I->isDebugValue())
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++I;
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unsigned NPredReg = 0;
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ARMCC::CondCodes NCC = getPredicate(I, NPredReg);
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if (NCC == CC || NCC == OCC)
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return true;
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}
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}
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return false;
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}
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bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
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bool Modified = false;
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SmallSet<unsigned, 4> Defs;
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SmallSet<unsigned, 4> Uses;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineInstr *MI = &*MBBI;
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DebugLoc dl = MI->getDebugLoc();
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unsigned PredReg = 0;
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ARMCC::CondCodes CC = getPredicate(MI, PredReg);
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if (CC == ARMCC::AL) {
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++MBBI;
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continue;
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}
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Defs.clear();
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Uses.clear();
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TrackDefUses(MI, Defs, Uses, TRI);
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// Insert an IT instruction.
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
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.addImm(CC);
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// Add implicit use of ITSTATE to IT block instructions.
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MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
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true/*isImp*/, false/*isKill*/));
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MachineInstr *LastITMI = MI;
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MachineBasicBlock::iterator InsertPos = MIB;
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++MBBI;
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// Form IT block.
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ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
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unsigned Mask = 0, Pos = 3;
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// Branches, including tricky ones like LDM_RET, need to end an IT
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// block so check the instruction we just put in the block.
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for (; MBBI != E && Pos &&
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(!MI->getDesc().isBranch() && !MI->getDesc().isReturn()) ; ++MBBI) {
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if (MBBI->isDebugValue())
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continue;
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MachineInstr *NMI = &*MBBI;
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MI = NMI;
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unsigned NPredReg = 0;
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ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
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if (NCC == CC || NCC == OCC) {
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Mask |= (NCC & 1) << Pos;
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// Add implicit use of ITSTATE.
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NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
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true/*isImp*/, false/*isKill*/));
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LastITMI = NMI;
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} else {
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if (NCC == ARMCC::AL &&
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MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
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--MBBI;
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MBB.remove(NMI);
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MBB.insert(InsertPos, NMI);
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++NumMovedInsts;
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continue;
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}
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break;
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}
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TrackDefUses(NMI, Defs, Uses, TRI);
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--Pos;
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}
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// Finalize IT mask.
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Mask |= (1 << Pos);
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// Tag along (firstcond[0] << 4) with the mask.
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Mask |= (CC & 1) << 4;
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MIB.addImm(Mask);
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// Last instruction in IT block kills ITSTATE.
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LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
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Modified = true;
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++NumITs;
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}
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return Modified;
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}
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bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
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const TargetMachine &TM = Fn.getTarget();
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AFI = Fn.getInfo<ARMFunctionInfo>();
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TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
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TRI = TM.getRegisterInfo();
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if (!AFI->isThumbFunction())
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return false;
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bool Modified = false;
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for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
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MachineBasicBlock &MBB = *MFI;
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++MFI;
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if (PreRegAlloc)
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Modified |= InsertITBlocks(MBB);
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else
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Modified |= InsertITInstructions(MBB);
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}
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if (Modified && !PreRegAlloc)
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AFI->setHasITBlocks(true);
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return Modified;
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}
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/// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
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/// insertion pass.
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FunctionPass *llvm::createThumb2ITBlockPass(bool PreAlloc) {
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return new Thumb2ITBlockPass(PreAlloc);
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}
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