llvm-6502/lib/Target/Sparc
Robin Morisset d310963833 Erase fence insertion from SelectionDAGBuilder.cpp (NFC)
Summary:
Backends can use setInsertFencesForAtomic to signal to the middle-end that
montonic is the only memory ordering they can accept for
stores/loads/rmws/cmpxchg. The code lowering those accesses with a stronger
ordering to fences + monotonic accesses is currently living in
SelectionDAGBuilder.cpp. In this patch I propose moving this logic out of it
for several reasons:
- There is lots of redundancy to avoid: extremely similar logic already
  exists in AtomicExpand.
- The current code in SelectionDAGBuilder does not use any target-hooks, it
  does the same transformation for every backend that requires it
- As a result it is plain *unsound*, as it was apparently designed for ARM.
  It happens to mostly work for the other targets because they are extremely
  conservative, but Power for example had to switch to AtomicExpand to be
  able to use lwsync safely (see r218331).
- Because it produces IR-level fences, it cannot be made sound ! This is noted
  in the C++11 standard (section 29.3, page 1140):
```
Fences cannot, in general, be used to restore sequential consistency for atomic
operations with weaker ordering semantics.
```
It can also be seen by the following example (called IRIW in the litterature):
```
atomic<int> x = y = 0;
int r1, r2, r3, r4;
Thread 0:
  x.store(1);
Thread 1:
  y.store(1);
Thread 2:
  r1 = x.load();
  r2 = y.load();
Thread 3:
  r3 = y.load();
  r4 = x.load();
```
r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst.
But if they are lowered to monotonic accesses, no amount of fences can prevent it..

This patch does three things (I could cut it into parts, but then some of them
would not be tested/testable, please tell me if you would prefer that):
- it provides a default implementation for emitLeadingFence/emitTrailingFence in
terms of IR-level fences, that mimic the original logic of SelectionDAGBuilder.
As we saw above, this is unsound, but the best that can be done without knowing
the targets well (and there is a comment warning about this risk).
- it then switches Mips/Sparc/XCore to use AtomicExpand, relying on this default
implementation (that exactly replicates the logic of SelectionDAGBuilder, so no
functional change)
- it finally erase this logic from SelectionDAGBuilder as it is dead-code.

Ideally, each target would define its own override for emitLeading/TrailingFence
using target-specific fences, but I do not know the Sparc/Mips/XCore memory model
well enough to do this, and they appear to be dealing fine with the ARM-inspired
default expansion for now (probably because they are overly conservative, as
Power was). If anyone wants to compile fences more agressively on these
platforms, the long comment should make it clear why he should first override
emitLeading/TrailingFence.

Test Plan: make check-all, no functional change

Reviewers: jfb, t.p.northover

Subscribers: aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D5474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219957 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-16 20:34:57 +00:00
..
AsmParser TableGen: allow use of uint64_t for available features mask. 2014-08-18 11:49:42 +00:00
Disassembler Prune dependency to MC from each target disassembler. 2014-07-24 11:45:11 +00:00
InstPrinter Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
MCTargetDesc Simplify handling of --noexecstack by using getNonexecutableStackSection. 2014-10-15 16:12:52 +00:00
TargetInfo Prune redundant dependencies in LLVMBuild.txt. 2013-12-11 00:30:57 +00:00
CMakeLists.txt Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
DelaySlotFiller.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
LLVMBuild.txt [Sparc] Add initial implementation of disassembler for sparc 2014-01-06 08:08:58 +00:00
Makefile Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
README.txt JIT support has been added awhile ago. 2014-08-30 14:52:34 +00:00
Sparc.h Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
Sparc.td [Sparc] Add VIS instructions to sparc backend. 2014-03-02 19:31:21 +00:00
SparcAsmPrinter.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
SparcCallingConv.td The SPARCv9 ABI returns a float in %f0. 2014-01-12 04:13:17 +00:00
SparcFrameLowering.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
SparcFrameLowering.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcInstr64Bit.td Sparc: disable printing on longer "brX,pt" aliases 2014-05-16 09:41:35 +00:00
SparcInstrAliases.td Sparc: disable printing of jmp/call aliases (C++ does it) 2014-05-16 09:41:39 +00:00
SparcInstrFormats.td [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend. 2014-03-02 23:39:07 +00:00
SparcInstrInfo.cpp Fix a lot of confusion around inserting nops on empty functions. 2014-09-15 18:32:58 +00:00
SparcInstrInfo.h Fix a lot of confusion around inserting nops on empty functions. 2014-09-15 18:32:58 +00:00
SparcInstrInfo.td Fix a whole bunch of binary literals which were the wrong size. All were being silently zero extended to the correct width. 2014-08-07 05:46:54 +00:00
SparcInstrVIS.td Fix a whole bunch of binary literals which were the wrong size. All were being silently zero extended to the correct width. 2014-08-07 05:46:54 +00:00
SparcISelDAGToDAG.cpp Cache TargetLowering on SelectionDAGISel and update previous 2014-10-08 07:32:17 +00:00
SparcISelLowering.cpp Remove the target machine from CCState. Previously it was only used 2014-08-06 18:45:26 +00:00
SparcISelLowering.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcMCInstLower.cpp [C++] Use 'nullptr'. Target edition. 2014-04-25 05:30:21 +00:00
SparcRegisterInfo.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
SparcRegisterInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcRegisterInfo.td [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3). 2014-03-02 02:12:33 +00:00
SparcSelectionDAGInfo.cpp Have SparcSelectionDAGInfo take a DataLayout to initialize since 2014-06-26 22:33:52 +00:00
SparcSelectionDAGInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcSubtarget.cpp Move the various Subtarget dependent members down to the subtarget 2014-06-26 22:33:55 +00:00
SparcSubtarget.h Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
SparcTargetMachine.cpp Erase fence insertion from SelectionDAGBuilder.cpp (NFC) 2014-10-16 20:34:57 +00:00
SparcTargetMachine.h Reverting NFC changes from r218050. Instead, the warning was disabled for GCC in r218059, so these changes are no longer required. 2014-09-18 17:34:23 +00:00
SparcTargetObjectFile.cpp [C++] Use 'nullptr'. Target edition. 2014-04-25 05:30:21 +00:00
SparcTargetObjectFile.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcTargetStreamer.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.