mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11151 91177308-0d34-0410-b5e6-96231b3b80d8
830 lines
30 KiB
C++
830 lines
30 KiB
C++
//===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a linear scan register allocator.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CFG.h"
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#include "Support/Debug.h"
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#include "Support/DepthFirstIterator.h"
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#include "Support/Statistic.h"
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#include "Support/STLExtras.h"
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using namespace llvm;
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namespace {
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Statistic<> numSpilled ("ra-linearscan", "Number of registers spilled");
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Statistic<> numReloaded("ra-linearscan", "Number of registers reloaded");
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Statistic<> numPeep ("ra-linearscan",
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"Number of identity moves eliminated");
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class PhysRegTracker {
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private:
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const MRegisterInfo* mri_;
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std::vector<bool> reserved_;
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std::vector<unsigned> regUse_;
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public:
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PhysRegTracker(MachineFunction* mf)
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: mri_(mf ? mf->getTarget().getRegisterInfo() : NULL) {
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if (mri_) {
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reserved_.assign(mri_->getNumRegs(), false);
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regUse_.assign(mri_->getNumRegs(), 0);
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}
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}
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PhysRegTracker(const PhysRegTracker& rhs)
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: mri_(rhs.mri_),
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reserved_(rhs.reserved_),
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regUse_(rhs.regUse_) {
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}
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const PhysRegTracker& operator=(const PhysRegTracker& rhs) {
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mri_ = rhs.mri_;
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reserved_ = rhs.reserved_;
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regUse_ = rhs.regUse_;
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return *this;
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}
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void reservePhysReg(unsigned physReg) {
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reserved_[physReg] = true;
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}
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void addPhysRegUse(unsigned physReg) {
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++regUse_[physReg];
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for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
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physReg = *as;
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++regUse_[physReg];
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}
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}
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void delPhysRegUse(unsigned physReg) {
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assert(regUse_[physReg] != 0);
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--regUse_[physReg];
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for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
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physReg = *as;
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assert(regUse_[physReg] != 0);
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--regUse_[physReg];
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}
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}
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bool isPhysRegReserved(unsigned physReg) const {
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return reserved_[physReg];
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}
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bool isPhysRegAvail(unsigned physReg) const {
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return regUse_[physReg] == 0 && !isPhysRegReserved(physReg);
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}
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bool isReservedPhysRegAvail(unsigned physReg) const {
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return regUse_[physReg] == 0 && isPhysRegReserved(physReg);
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}
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};
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class RA : public MachineFunctionPass {
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private:
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MachineFunction* mf_;
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const TargetMachine* tm_;
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const MRegisterInfo* mri_;
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LiveIntervals* li_;
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MachineFunction::iterator currentMbb_;
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MachineBasicBlock::iterator currentInstr_;
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typedef std::vector<const LiveIntervals::Interval*> IntervalPtrs;
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IntervalPtrs unhandled_, fixed_, active_, inactive_;
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PhysRegTracker prt_;
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typedef std::map<unsigned, unsigned> Virt2PhysMap;
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Virt2PhysMap v2pMap_;
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typedef std::map<unsigned, int> Virt2StackSlotMap;
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Virt2StackSlotMap v2ssMap_;
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int instrAdded_;
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typedef std::vector<float> SpillWeights;
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SpillWeights spillWeights_;
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public:
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RA()
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: prt_(NULL) {
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}
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virtual const char* getPassName() const {
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return "Linear Scan Register Allocator";
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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AU.addRequired<LiveIntervals>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - register allocate the whole function
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bool runOnMachineFunction(MachineFunction&);
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void releaseMemory();
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private:
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/// initIntervalSets - initializa the four interval sets:
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/// unhandled, fixed, active and inactive
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void initIntervalSets(const LiveIntervals::Intervals& li);
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/// processActiveIntervals - expire old intervals and move
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/// non-overlapping ones to the incative list
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void processActiveIntervals(IntervalPtrs::value_type cur);
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/// processInactiveIntervals - expire old intervals and move
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/// overlapping ones to the active list
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void processInactiveIntervals(IntervalPtrs::value_type cur);
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/// updateSpillWeights - updates the spill weights of the
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/// specifed physical register and its weight
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void updateSpillWeights(unsigned reg, SpillWeights::value_type weight);
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/// assignRegOrStackSlotAtInterval - assign a register if one
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/// is available, or spill.
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void assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur);
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///
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/// register handling helpers
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///
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/// getFreePhysReg - return a free physical register for this
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/// virtual register interval if we have one, otherwise return
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/// 0
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unsigned getFreePhysReg(IntervalPtrs::value_type cur);
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/// getFreeTempPhysReg - return a free temprorary physical
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/// register for this virtual register if we have one (should
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/// never return 0)
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unsigned getFreeTempPhysReg(unsigned virtReg);
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/// assignVirt2PhysReg - assigns the free physical register to
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/// the virtual register passed as arguments
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Virt2PhysMap::iterator
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assignVirt2PhysReg(unsigned virtReg, unsigned physReg);
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/// clearVirtReg - free the physical register associated with this
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/// virtual register and disassociate virtual->physical and
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/// physical->virtual mappings
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void clearVirtReg(Virt2PhysMap::iterator it);
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/// assignVirt2StackSlot - assigns this virtual register to a
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/// stack slot
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void assignVirt2StackSlot(unsigned virtReg);
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/// getStackSlot - returns the offset of the specified
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/// register on the stack
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int getStackSlot(unsigned virtReg);
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/// spillVirtReg - spills the virtual register
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void spillVirtReg(Virt2PhysMap::iterator it);
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/// loadPhysReg - loads to the physical register the value of
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/// the virtual register specifed. Virtual register must have
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/// an assigned stack slot
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Virt2PhysMap::iterator
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loadVirt2PhysReg(unsigned virtReg, unsigned physReg);
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void printVirtRegAssignment() const {
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std::cerr << "register assignment:\n";
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for (Virt2PhysMap::const_iterator
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i = v2pMap_.begin(), e = v2pMap_.end(); i != e; ++i) {
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assert(i->second != 0);
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std::cerr << '[' << i->first << ','
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<< mri_->getName(i->second) << "]\n";
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}
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for (Virt2StackSlotMap::const_iterator
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i = v2ssMap_.begin(), e = v2ssMap_.end(); i != e; ++i) {
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std::cerr << '[' << i->first << ",ss#" << i->second << "]\n";
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}
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std::cerr << '\n';
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}
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void printIntervals(const char* const str,
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RA::IntervalPtrs::const_iterator i,
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RA::IntervalPtrs::const_iterator e) const {
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if (str) std::cerr << str << " intervals:\n";
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for (; i != e; ++i) {
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std::cerr << "\t\t" << **i << " -> ";
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unsigned reg = (*i)->reg;
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if (MRegisterInfo::isVirtualRegister(reg)) {
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Virt2PhysMap::const_iterator it = v2pMap_.find(reg);
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reg = (it == v2pMap_.end() ? 0 : it->second);
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}
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std::cerr << mri_->getName(reg) << '\n';
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}
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}
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// void printFreeRegs(const char* const str,
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// const TargetRegisterClass* rc) const {
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// if (str) std::cerr << str << ':';
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// for (TargetRegisterClass::iterator i =
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// rc->allocation_order_begin(*mf_);
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// i != rc->allocation_order_end(*mf_); ++i) {
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// unsigned reg = *i;
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// if (!regUse_[reg]) {
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// std::cerr << ' ' << mri_->getName(reg);
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// if (reserved_[reg]) std::cerr << "*";
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// }
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// }
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// std::cerr << '\n';
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// }
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};
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}
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void RA::releaseMemory()
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{
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v2pMap_.clear();
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v2ssMap_.clear();
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unhandled_.clear();
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active_.clear();
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inactive_.clear();
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fixed_.clear();
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}
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bool RA::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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tm_ = &fn.getTarget();
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mri_ = tm_->getRegisterInfo();
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li_ = &getAnalysis<LiveIntervals>();
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prt_ = PhysRegTracker(mf_);
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initIntervalSets(li_->getIntervals());
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// FIXME: this will work only for the X86 backend. I need to
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// device an algorthm to select the minimal (considering register
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// aliasing) number of temp registers to reserve so that we have 2
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// registers for each register class available.
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// reserve R8: CH, CL
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// R16: CX, DI,
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// R32: ECX, EDI,
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// RFP: FP5, FP6
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prt_.reservePhysReg( 8); /* CH */
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prt_.reservePhysReg( 9); /* CL */
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prt_.reservePhysReg(10); /* CX */
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prt_.reservePhysReg(12); /* DI */
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prt_.reservePhysReg(18); /* ECX */
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prt_.reservePhysReg(19); /* EDI */
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prt_.reservePhysReg(28); /* FP5 */
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prt_.reservePhysReg(29); /* FP6 */
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// linear scan algorithm
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DEBUG(std::cerr << "Machine Function\n");
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DEBUG(printIntervals("\tunhandled", unhandled_.begin(), unhandled_.end()));
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DEBUG(printIntervals("\tfixed", fixed_.begin(), fixed_.end()));
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DEBUG(printIntervals("\tactive", active_.begin(), active_.end()));
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DEBUG(printIntervals("\tinactive", inactive_.begin(), inactive_.end()));
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while (!unhandled_.empty() || !fixed_.empty()) {
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// pick the interval with the earliest start point
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IntervalPtrs::value_type cur;
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if (fixed_.empty()) {
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cur = unhandled_.front();
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unhandled_.erase(unhandled_.begin());
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}
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else if (unhandled_.empty()) {
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cur = fixed_.front();
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fixed_.erase(fixed_.begin());
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}
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else if (unhandled_.front()->start() < fixed_.front()->start()) {
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cur = unhandled_.front();
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unhandled_.erase(unhandled_.begin());
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}
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else {
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cur = fixed_.front();
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fixed_.erase(fixed_.begin());
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}
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DEBUG(std::cerr << *cur << '\n');
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processActiveIntervals(cur);
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processInactiveIntervals(cur);
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// if this register is fixed we are done
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if (MRegisterInfo::isPhysicalRegister(cur->reg)) {
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prt_.addPhysRegUse(cur->reg);
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active_.push_back(cur);
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}
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// otherwise we are allocating a virtual register. try to find
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// a free physical register or spill an interval in order to
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// assign it one (we could spill the current though).
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else {
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assignRegOrStackSlotAtInterval(cur);
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}
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DEBUG(printIntervals("\tactive", active_.begin(), active_.end()));
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DEBUG(printIntervals("\tinactive", inactive_.begin(), inactive_.end())); }
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// expire any remaining active intervals
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for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
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unsigned reg = (*i)->reg;
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DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
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if (MRegisterInfo::isVirtualRegister(reg)) {
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reg = v2pMap_[reg];
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}
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prt_.delPhysRegUse(reg);
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}
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typedef LiveIntervals::Reg2RegMap Reg2RegMap;
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const Reg2RegMap& r2rMap = li_->getJoinedRegMap();
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DEBUG(printVirtRegAssignment());
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DEBUG(std::cerr << "Performing coalescing on joined intervals\n");
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// perform coalescing if we were passed joined intervals
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for(Reg2RegMap::const_iterator i = r2rMap.begin(), e = r2rMap.end();
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i != e; ++i) {
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unsigned reg = i->first;
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unsigned rep = li_->rep(reg);
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assert((MRegisterInfo::isPhysicalRegister(rep) ||
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v2pMap_.count(rep) || v2ssMap_.count(rep)) &&
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"representative register is not allocated!");
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assert(MRegisterInfo::isVirtualRegister(reg) &&
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!v2pMap_.count(reg) && !v2ssMap_.count(reg) &&
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"coalesced register is already allocated!");
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if (MRegisterInfo::isPhysicalRegister(rep)) {
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v2pMap_.insert(std::make_pair(reg, rep));
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}
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else {
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Virt2PhysMap::const_iterator pr = v2pMap_.find(rep);
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if (pr != v2pMap_.end()) {
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v2pMap_.insert(std::make_pair(reg, pr->second));
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}
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else {
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Virt2StackSlotMap::const_iterator ss = v2ssMap_.find(rep);
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assert(ss != v2ssMap_.end());
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v2ssMap_.insert(std::make_pair(reg, ss->second));
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}
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}
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}
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DEBUG(printVirtRegAssignment());
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DEBUG(std::cerr << "finished register allocation\n");
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const TargetInstrInfo& tii = tm_->getInstrInfo();
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DEBUG(std::cerr << "Rewrite machine code:\n");
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for (currentMbb_ = mf_->begin(); currentMbb_ != mf_->end(); ++currentMbb_) {
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instrAdded_ = 0;
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for (currentInstr_ = currentMbb_->begin();
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currentInstr_ != currentMbb_->end(); ) {
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DEBUG(std::cerr << "\tinstruction: ";
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(*currentInstr_)->print(std::cerr, *tm_););
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// use our current mapping and actually replace and
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// virtual register with its allocated physical registers
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DEBUG(std::cerr << "\t\treplacing virtual registers with mapped "
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"physical registers:\n");
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for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
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i != e; ++i) {
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MachineOperand& op = (*currentInstr_)->getOperand(i);
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if (op.isVirtualRegister()) {
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unsigned virtReg = op.getAllocatedRegNum();
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Virt2PhysMap::const_iterator it = v2pMap_.find(virtReg);
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if (it != v2pMap_.end()) {
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DEBUG(std::cerr << "\t\t\t%reg" << it->first
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<< " -> " << mri_->getName(it->second) << '\n');
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(*currentInstr_)->SetMachineOperandReg(i, it->second);
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}
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}
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}
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unsigned srcReg, dstReg;
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if (tii.isMoveInstr(**currentInstr_, srcReg, dstReg) &&
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((MRegisterInfo::isPhysicalRegister(srcReg) &&
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MRegisterInfo::isPhysicalRegister(dstReg) &&
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srcReg == dstReg) ||
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(MRegisterInfo::isVirtualRegister(srcReg) &&
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MRegisterInfo::isVirtualRegister(dstReg) &&
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v2ssMap_[srcReg] == v2ssMap_[dstReg]))) {
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delete *currentInstr_;
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currentInstr_ = currentMbb_->erase(currentInstr_);
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++numPeep;
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DEBUG(std::cerr << "\t\tdeleting instruction\n");
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continue;
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}
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typedef std::vector<Virt2PhysMap::iterator> Regs;
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Regs toClear;
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Regs toSpill;
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const unsigned numOperands = (*currentInstr_)->getNumOperands();
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DEBUG(std::cerr << "\t\tloading temporarily used operands to "
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"registers:\n");
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for (unsigned i = 0; i != numOperands; ++i) {
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MachineOperand& op = (*currentInstr_)->getOperand(i);
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if (op.isVirtualRegister() && op.isUse()) {
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unsigned virtReg = op.getAllocatedRegNum();
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unsigned physReg = 0;
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Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
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if (it != v2pMap_.end()) {
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physReg = it->second;
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}
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else {
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physReg = getFreeTempPhysReg(virtReg);
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it = loadVirt2PhysReg(virtReg, physReg);
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// we will clear uses that are not also defs
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// before we allocate registers the defs
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if (op.isDef())
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toSpill.push_back(it);
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else
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toClear.push_back(it);
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}
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(*currentInstr_)->SetMachineOperandReg(i, physReg);
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}
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}
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DEBUG(std::cerr << "\t\tclearing temporarily used but not defined "
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"operands:\n");
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std::for_each(toClear.begin(), toClear.end(),
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std::bind1st(std::mem_fun(&RA::clearVirtReg), this));
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DEBUG(std::cerr << "\t\tassigning temporarily defined operands to "
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"registers:\n");
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for (unsigned i = 0; i != numOperands; ++i) {
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MachineOperand& op = (*currentInstr_)->getOperand(i);
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if (op.isVirtualRegister()) {
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assert(!op.isUse() && "we should not have uses here!");
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unsigned virtReg = op.getAllocatedRegNum();
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unsigned physReg = 0;
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Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
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if (it != v2pMap_.end()) {
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physReg = it->second;
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}
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else {
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physReg = getFreeTempPhysReg(virtReg);
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it = assignVirt2PhysReg(virtReg, physReg);
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// need to spill this after we are done with
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// this instruction
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toSpill.push_back(it);
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}
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(*currentInstr_)->SetMachineOperandReg(i, physReg);
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}
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}
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++currentInstr_; // spills will go after this instruction
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DEBUG(std::cerr << "\t\tspilling temporarily defined operands:\n");
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std::for_each(toSpill.begin(), toSpill.end(),
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std::bind1st(std::mem_fun(&RA::spillVirtReg), this));
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
void RA::initIntervalSets(const LiveIntervals::Intervals& li)
|
|
{
|
|
assert(unhandled_.empty() && fixed_.empty() &&
|
|
active_.empty() && inactive_.empty() &&
|
|
"interval sets should be empty on initialization");
|
|
|
|
for (LiveIntervals::Intervals::const_iterator i = li.begin(), e = li.end();
|
|
i != e; ++i) {
|
|
if (MRegisterInfo::isPhysicalRegister(i->reg))
|
|
fixed_.push_back(&*i);
|
|
else
|
|
unhandled_.push_back(&*i);
|
|
}
|
|
}
|
|
|
|
void RA::processActiveIntervals(IntervalPtrs::value_type cur)
|
|
{
|
|
DEBUG(std::cerr << "\tprocessing active intervals:\n");
|
|
for (IntervalPtrs::iterator i = active_.begin(); i != active_.end();) {
|
|
unsigned reg = (*i)->reg;
|
|
// remove expired intervals
|
|
if ((*i)->expiredAt(cur->start())) {
|
|
DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
|
|
if (MRegisterInfo::isVirtualRegister(reg)) {
|
|
reg = v2pMap_[reg];
|
|
}
|
|
prt_.delPhysRegUse(reg);
|
|
// remove from active
|
|
i = active_.erase(i);
|
|
}
|
|
// move inactive intervals to inactive list
|
|
else if (!(*i)->liveAt(cur->start())) {
|
|
DEBUG(std::cerr << "\t\t\tinterval " << **i << " inactive\n");
|
|
if (MRegisterInfo::isVirtualRegister(reg)) {
|
|
reg = v2pMap_[reg];
|
|
}
|
|
prt_.delPhysRegUse(reg);
|
|
// add to inactive
|
|
inactive_.push_back(*i);
|
|
// remove from active
|
|
i = active_.erase(i);
|
|
}
|
|
else {
|
|
++i;
|
|
}
|
|
}
|
|
}
|
|
|
|
void RA::processInactiveIntervals(IntervalPtrs::value_type cur)
|
|
{
|
|
DEBUG(std::cerr << "\tprocessing inactive intervals:\n");
|
|
for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end();) {
|
|
unsigned reg = (*i)->reg;
|
|
|
|
// remove expired intervals
|
|
if ((*i)->expiredAt(cur->start())) {
|
|
DEBUG(std::cerr << "\t\t\tinterval " << **i << " expired\n");
|
|
// remove from inactive
|
|
i = inactive_.erase(i);
|
|
}
|
|
// move re-activated intervals in active list
|
|
else if ((*i)->liveAt(cur->start())) {
|
|
DEBUG(std::cerr << "\t\t\tinterval " << **i << " active\n");
|
|
if (MRegisterInfo::isVirtualRegister(reg)) {
|
|
reg = v2pMap_[reg];
|
|
}
|
|
prt_.addPhysRegUse(reg);
|
|
// add to active
|
|
active_.push_back(*i);
|
|
// remove from inactive
|
|
i = inactive_.erase(i);
|
|
}
|
|
else {
|
|
++i;
|
|
}
|
|
}
|
|
}
|
|
|
|
void RA::updateSpillWeights(unsigned reg, SpillWeights::value_type weight)
|
|
{
|
|
spillWeights_[reg] += weight;
|
|
for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as)
|
|
spillWeights_[*as] += weight;
|
|
}
|
|
|
|
void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
|
|
{
|
|
DEBUG(std::cerr << "\tallocating current interval:\n");
|
|
|
|
PhysRegTracker backupPrt = prt_;
|
|
|
|
spillWeights_.assign(mri_->getNumRegs(), 0.0);
|
|
|
|
// for each interval in active update spill weights
|
|
for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
|
|
i != e; ++i) {
|
|
unsigned reg = (*i)->reg;
|
|
if (MRegisterInfo::isVirtualRegister(reg))
|
|
reg = v2pMap_[reg];
|
|
updateSpillWeights(reg, (*i)->weight);
|
|
}
|
|
|
|
// for every interval in inactive we overlap with, mark the
|
|
// register as not free and update spill weights
|
|
for (IntervalPtrs::const_iterator i = inactive_.begin(),
|
|
e = inactive_.end(); i != e; ++i) {
|
|
if (cur->overlaps(**i)) {
|
|
unsigned reg = (*i)->reg;
|
|
if (MRegisterInfo::isVirtualRegister(reg))
|
|
reg = v2pMap_[reg];
|
|
prt_.addPhysRegUse(reg);
|
|
updateSpillWeights(reg, (*i)->weight);
|
|
}
|
|
}
|
|
|
|
// for every interval in fixed we overlap with,
|
|
// mark the register as not free and update spill weights
|
|
for (IntervalPtrs::const_iterator i = fixed_.begin(),
|
|
e = fixed_.end(); i != e; ++i) {
|
|
if (cur->overlaps(**i)) {
|
|
unsigned reg = (*i)->reg;
|
|
prt_.addPhysRegUse(reg);
|
|
updateSpillWeights(reg, (*i)->weight);
|
|
}
|
|
}
|
|
|
|
unsigned physReg = getFreePhysReg(cur);
|
|
// if we find a free register, we are done: restore original
|
|
// register tracker, assign this virtual to the free physical
|
|
// register and add this interval to the active list.
|
|
if (physReg) {
|
|
prt_ = backupPrt;
|
|
assignVirt2PhysReg(cur->reg, physReg);
|
|
active_.push_back(cur);
|
|
return;
|
|
}
|
|
|
|
DEBUG(std::cerr << "\t\tassigning stack slot at interval "<< *cur << ":\n");
|
|
|
|
float minWeight = std::numeric_limits<float>::max();
|
|
unsigned minReg = 0;
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
|
|
for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
|
|
i != rc->allocation_order_end(*mf_); ++i) {
|
|
unsigned reg = *i;
|
|
if (!prt_.isPhysRegReserved(reg) && minWeight > spillWeights_[reg]) {
|
|
minWeight = spillWeights_[reg];
|
|
minReg = reg;
|
|
}
|
|
}
|
|
DEBUG(std::cerr << "\t\t\tregister with min weight: "
|
|
<< mri_->getName(minReg) << " (" << minWeight << ")\n");
|
|
|
|
// if the current has the minimum weight, we are done: restore
|
|
// original register tracker and assign a stack slot to this
|
|
// virtual register
|
|
if (cur->weight < minWeight) {
|
|
prt_ = backupPrt;
|
|
DEBUG(std::cerr << "\t\t\t\tspilling: " << *cur << '\n');
|
|
assignVirt2StackSlot(cur->reg);
|
|
return;
|
|
}
|
|
|
|
std::vector<bool> toSpill(mri_->getNumRegs(), false);
|
|
toSpill[minReg] = true;
|
|
for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as)
|
|
toSpill[*as] = true;
|
|
|
|
std::vector<unsigned> spilled;
|
|
for (IntervalPtrs::iterator i = active_.begin();
|
|
i != active_.end(); ) {
|
|
unsigned reg = (*i)->reg;
|
|
if (MRegisterInfo::isVirtualRegister(reg) &&
|
|
toSpill[v2pMap_[reg]] &&
|
|
cur->overlaps(**i)) {
|
|
spilled.push_back(v2pMap_[reg]);
|
|
DEBUG(std::cerr << "\t\t\t\tspilling : " << **i << '\n');
|
|
assignVirt2StackSlot(reg);
|
|
i = active_.erase(i);
|
|
}
|
|
else {
|
|
++i;
|
|
}
|
|
}
|
|
for (IntervalPtrs::iterator i = inactive_.begin();
|
|
i != inactive_.end(); ) {
|
|
unsigned reg = (*i)->reg;
|
|
if (MRegisterInfo::isVirtualRegister(reg) &&
|
|
toSpill[v2pMap_[reg]] &&
|
|
cur->overlaps(**i)) {
|
|
DEBUG(std::cerr << "\t\t\t\tspilling : " << **i << '\n');
|
|
assignVirt2StackSlot(reg);
|
|
i = inactive_.erase(i);
|
|
}
|
|
else {
|
|
++i;
|
|
}
|
|
}
|
|
|
|
physReg = getFreePhysReg(cur);
|
|
assert(physReg && "no free physical register after spill?");
|
|
|
|
prt_ = backupPrt;
|
|
for (unsigned i = 0; i < spilled.size(); ++i)
|
|
prt_.delPhysRegUse(spilled[i]);
|
|
|
|
assignVirt2PhysReg(cur->reg, physReg);
|
|
active_.push_back(cur);
|
|
}
|
|
|
|
unsigned RA::getFreePhysReg(IntervalPtrs::value_type cur)
|
|
{
|
|
DEBUG(std::cerr << "\t\tgetting free physical register: ");
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
|
|
|
|
for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
|
|
i != rc->allocation_order_end(*mf_); ++i) {
|
|
unsigned reg = *i;
|
|
if (prt_.isPhysRegAvail(reg)) {
|
|
DEBUG(std::cerr << mri_->getName(reg) << '\n');
|
|
return reg;
|
|
}
|
|
}
|
|
|
|
DEBUG(std::cerr << "no free register\n");
|
|
return 0;
|
|
}
|
|
|
|
unsigned RA::getFreeTempPhysReg(unsigned virtReg)
|
|
{
|
|
DEBUG(std::cerr << "\t\tgetting free temporary physical register: ");
|
|
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
|
|
// go in reverse allocation order for the temp registers
|
|
typedef std::reverse_iterator<TargetRegisterClass::iterator> TRCRevIter;
|
|
for (TRCRevIter
|
|
i(rc->allocation_order_end(*mf_)),
|
|
e(rc->allocation_order_begin(*mf_)); i != e; ++i) {
|
|
unsigned reg = *i;
|
|
if (prt_.isReservedPhysRegAvail(reg)) {
|
|
DEBUG(std::cerr << mri_->getName(reg) << '\n');
|
|
return reg;
|
|
}
|
|
}
|
|
|
|
assert(0 && "no free temporary physical register?");
|
|
return 0;
|
|
}
|
|
|
|
RA::Virt2PhysMap::iterator
|
|
RA::assignVirt2PhysReg(unsigned virtReg, unsigned physReg)
|
|
{
|
|
bool inserted;
|
|
Virt2PhysMap::iterator it;
|
|
tie(it, inserted) = v2pMap_.insert(std::make_pair(virtReg, physReg));
|
|
assert(inserted && "attempting to assign a virt->phys mapping to an "
|
|
"already mapped register");
|
|
prt_.addPhysRegUse(physReg);
|
|
return it;
|
|
}
|
|
|
|
void RA::clearVirtReg(Virt2PhysMap::iterator it)
|
|
{
|
|
assert(it != v2pMap_.end() &&
|
|
"attempting to clear a not allocated virtual register");
|
|
unsigned physReg = it->second;
|
|
prt_.delPhysRegUse(physReg);
|
|
v2pMap_.erase(it);
|
|
DEBUG(std::cerr << "\t\t\tcleared register " << mri_->getName(physReg)
|
|
<< "\n");
|
|
}
|
|
|
|
void RA::assignVirt2StackSlot(unsigned virtReg)
|
|
{
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
|
|
int frameIndex = mf_->getFrameInfo()->CreateStackObject(rc);
|
|
|
|
bool inserted = v2ssMap_.insert(std::make_pair(virtReg, frameIndex)).second;
|
|
assert(inserted &&
|
|
"attempt to assign stack slot to already assigned register?");
|
|
// if the virtual register was previously assigned clear the mapping
|
|
// and free the virtual register
|
|
Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
|
|
if (it != v2pMap_.end()) {
|
|
clearVirtReg(it);
|
|
}
|
|
}
|
|
|
|
int RA::getStackSlot(unsigned virtReg)
|
|
{
|
|
Virt2StackSlotMap::iterator it = v2ssMap_.find(virtReg);
|
|
assert(it != v2ssMap_.end() &&
|
|
"attempt to get stack slot on register that does not live on the stack");
|
|
return it->second;
|
|
}
|
|
|
|
void RA::spillVirtReg(Virt2PhysMap::iterator it)
|
|
{
|
|
assert(it != v2pMap_.end() &&
|
|
"attempt to spill a not allocated virtual register");
|
|
unsigned virtReg = it->first;
|
|
DEBUG(std::cerr << "\t\t\tspilling register: " << virtReg);
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
|
|
int frameIndex = getStackSlot(virtReg);
|
|
DEBUG(std::cerr << " to stack slot #" << frameIndex << '\n');
|
|
++numSpilled;
|
|
instrAdded_ += mri_->storeRegToStackSlot(*currentMbb_, currentInstr_,
|
|
it->second, frameIndex, rc);
|
|
clearVirtReg(it);
|
|
}
|
|
|
|
RA::Virt2PhysMap::iterator
|
|
RA::loadVirt2PhysReg(unsigned virtReg, unsigned physReg)
|
|
{
|
|
DEBUG(std::cerr << "\t\t\tloading register: " << virtReg);
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
|
|
int frameIndex = getStackSlot(virtReg);
|
|
DEBUG(std::cerr << " from stack slot #" << frameIndex << '\n');
|
|
++numReloaded;
|
|
instrAdded_ += mri_->loadRegFromStackSlot(*currentMbb_, currentInstr_,
|
|
physReg, frameIndex, rc);
|
|
return assignVirt2PhysReg(virtReg, physReg);
|
|
}
|
|
|
|
FunctionPass* llvm::createLinearScanRegisterAllocator() {
|
|
return new RA();
|
|
}
|