mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-21 06:30:16 +00:00
c3e70ca886
Some ICmpInsts when anded/ored with another ICmpInst trivially reduces to true or false depending on whether or not all integers or no integers satisfy the intersected/unioned range. This sort of trivial looking code can come about when InstCombine performs a range reduction-type operation on sdiv and the like. This fixes PR20916. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217750 91177308-0d34-0410-b5e6-96231b3b80d8
151 lines
3.0 KiB
LLVM
151 lines
3.0 KiB
LLVM
; RUN: opt < %s -instsimplify -S | FileCheck %s
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define i64 @pow2(i32 %x) {
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; CHECK-LABEL: @pow2(
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%negx = sub i32 0, %x
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%x2 = and i32 %x, %negx
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%e = zext i32 %x2 to i64
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%nege = sub i64 0, %e
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%e2 = and i64 %e, %nege
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ret i64 %e2
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; CHECK: ret i64 %e
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}
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define i64 @pow2b(i32 %x) {
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; CHECK-LABEL: @pow2b(
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%sh = shl i32 2, %x
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%e = zext i32 %sh to i64
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%nege = sub i64 0, %e
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%e2 = and i64 %e, %nege
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ret i64 %e2
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; CHECK: ret i64 %e
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}
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define i32 @sub_neg_nuw(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_neg_nuw(
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%neg = sub nuw i32 0, %y
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%sub = sub i32 %x, %neg
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ret i32 %sub
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; CHECK: ret i32 %x
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}
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define i1 @and_of_icmps0(i32 %b) {
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; CHECK-LABEL: @and_of_icmps0(
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%1 = add i32 %b, 2
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%2 = icmp ult i32 %1, 4
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%cmp3 = icmp sgt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 false
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}
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define i1 @and_of_icmps1(i32 %b) {
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; CHECK-LABEL: @and_of_icmps1(
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%1 = add nsw i32 %b, 2
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%2 = icmp slt i32 %1, 4
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%cmp3 = icmp sgt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 false
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}
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define i1 @and_of_icmps2(i32 %b) {
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; CHECK-LABEL: @and_of_icmps2(
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%1 = add i32 %b, 2
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%2 = icmp ule i32 %1, 3
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%cmp3 = icmp sgt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 false
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}
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define i1 @and_of_icmps3(i32 %b) {
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; CHECK-LABEL: @and_of_icmps3(
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%1 = add nsw i32 %b, 2
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%2 = icmp sle i32 %1, 3
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%cmp3 = icmp sgt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 false
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}
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define i1 @and_of_icmps4(i32 %b) {
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; CHECK-LABEL: @and_of_icmps4(
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%1 = add nuw i32 %b, 2
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%2 = icmp ult i32 %1, 4
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%cmp3 = icmp ugt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 false
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}
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define i1 @and_of_icmps5(i32 %b) {
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; CHECK-LABEL: @and_of_icmps5(
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%1 = add nuw i32 %b, 2
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%2 = icmp ule i32 %1, 3
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%cmp3 = icmp ugt i32 %b, 2
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%cmp = and i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 false
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}
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define i1 @or_of_icmps0(i32 %b) {
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; CHECK-LABEL: @or_of_icmps0(
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%1 = add i32 %b, 2
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%2 = icmp uge i32 %1, 4
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%cmp3 = icmp sle i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 true
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}
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define i1 @or_of_icmps1(i32 %b) {
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; CHECK-LABEL: @or_of_icmps1(
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%1 = add nsw i32 %b, 2
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%2 = icmp sge i32 %1, 4
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%cmp3 = icmp sle i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 true
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}
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define i1 @or_of_icmps2(i32 %b) {
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; CHECK-LABEL: @or_of_icmps2(
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%1 = add i32 %b, 2
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%2 = icmp ugt i32 %1, 3
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%cmp3 = icmp sle i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 true
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}
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define i1 @or_of_icmps3(i32 %b) {
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; CHECK-LABEL: @or_of_icmps3(
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%1 = add nsw i32 %b, 2
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%2 = icmp sgt i32 %1, 3
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%cmp3 = icmp sle i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 true
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}
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define i1 @or_of_icmps4(i32 %b) {
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; CHECK-LABEL: @or_of_icmps4(
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%1 = add nuw i32 %b, 2
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%2 = icmp uge i32 %1, 4
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%cmp3 = icmp ule i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 true
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}
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define i1 @or_of_icmps5(i32 %b) {
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; CHECK-LABEL: @or_of_icmps5(
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%1 = add nuw i32 %b, 2
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%2 = icmp ugt i32 %1, 3
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%cmp3 = icmp ule i32 %b, 2
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%cmp = or i1 %2, %cmp3
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ret i1 %cmp
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; CHECK: ret i1 true
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}
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