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https://github.com/c64scene-ar/llvm-6502.git
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e7bd51980a
registers. Previously, the register we being marked as implicitly defined, but not killed. In some cases this would cause the register scavenger to spill a dead register. Also, use an empty register mask to simplify the logic and to reduce the memory footprint. rdar://12592448 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167499 91177308-0d34-0410-b5e6-96231b3b80d8
207 lines
8.5 KiB
TableGen
207 lines
8.5 KiB
TableGen
//===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for ARM architecture.
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//===----------------------------------------------------------------------===//
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/// CCIfAlign - Match of the original alignment of the arg
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class CCIfAlign<string Align, CCAction A>:
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CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
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//===----------------------------------------------------------------------===//
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// ARM APCS Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_ARM_APCS : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<4, 4>>,
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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// f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
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CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
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CCIfType<[f32], CCBitConvertToType<i32>>,
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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CCIfType<[i32], CCAssignToStack<4, 4>>,
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CCIfType<[f64], CCAssignToStack<8, 4>>,
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CCIfType<[v2f64], CCAssignToStack<16, 4>>
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]>;
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def RetCC_ARM_APCS : CallingConv<[
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[f32], CCBitConvertToType<i32>>,
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
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//===----------------------------------------------------------------------===//
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def FastCC_ARM_APCS : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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CCDelegateTo<CC_ARM_APCS>
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]>;
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def RetFastCC_ARM_APCS : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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CCDelegateTo<RetCC_ARM_APCS>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM APCS Calling Convention for GHC
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//===----------------------------------------------------------------------===//
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def CC_ARM_APCS_GHC : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
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CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
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CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
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CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM AAPCS (EABI) Calling Convention, common parts
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//===----------------------------------------------------------------------===//
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def CC_ARM_AAPCS_Common : CallingConv<[
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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// i64/f64 is passed in even pairs of GPRs
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// i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
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// (and the same is true for f64 if VFP is not enabled)
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CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
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CCIfType<[i32], CCIf<"State.getNextStackOffset() == 0 &&"
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"ArgFlags.getOrigAlign() != 8",
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CCAssignToReg<[R0, R1, R2, R3]>>>,
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CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, R3>>>,
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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CCIfType<[f64], CCAssignToStack<8, 8>>,
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CCIfType<[v2f64], CCAssignToStack<16, 8>>
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]>;
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def RetCC_ARM_AAPCS_Common : CallingConv<[
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM AAPCS (EABI) Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_ARM_AAPCS : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<4, 4>>,
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
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CCIfType<[f32], CCBitConvertToType<i32>>,
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CCDelegateTo<CC_ARM_AAPCS_Common>
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]>;
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def RetCC_ARM_AAPCS : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
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CCIfType<[f32], CCBitConvertToType<i32>>,
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CCDelegateTo<RetCC_ARM_AAPCS_Common>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM AAPCS-VFP (EABI) Calling Convention
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// Also used for FastCC (when VFP2 or later is available)
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//===----------------------------------------------------------------------===//
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def CC_ARM_AAPCS_VFP : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<4, 4>>,
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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CCDelegateTo<CC_ARM_AAPCS_Common>
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]>;
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def RetCC_ARM_AAPCS_VFP : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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CCDelegateTo<RetCC_ARM_AAPCS_Common>
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]>;
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//===----------------------------------------------------------------------===//
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// Callee-saved register lists.
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//===----------------------------------------------------------------------===//
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
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(sequence "D%u", 15, 8))>;
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// iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
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// Also save R7-R4 first to match the stack frame fixed spill areas.
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def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
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// GHC set of callee saved regs is empty as all those regs are
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// used for passing STG regs around
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// add is a workaround for not being able to compile empty list:
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// def CSR_GHC : CalleeSavedRegs<()>;
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def CSR_GHC : CalleeSavedRegs<(add)>;
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