mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
563 lines
15 KiB
C++
563 lines
15 KiB
C++
//===-- MBlazeAsmParser.cpp - Parse MBlaze asm to MCInst instructions -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/MBlazeBaseInfo.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Twine.h"
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using namespace llvm;
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namespace {
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struct MBlazeOperand;
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class MBlazeAsmParser : public MCTargetAsmParser {
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MCAsmParser &Parser;
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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MBlazeOperand *ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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MBlazeOperand *ParseRegister(unsigned &RegNo);
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MBlazeOperand *ParseImmediate();
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MBlazeOperand *ParseFsl();
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MBlazeOperand* ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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bool MatchAndEmitInstruction(SMLoc IDLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out);
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/// @name Auto-generated Match Functions
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/// {
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#define GET_ASSEMBLER_HEADER
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#include "MBlazeGenAsmMatcher.inc"
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/// }
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public:
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MBlazeAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
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: MCTargetAsmParser(), Parser(_Parser) {}
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virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseDirective(AsmToken DirectiveID);
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};
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/// MBlazeOperand - Instances of this class represent a parsed MBlaze machine
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/// instruction.
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struct MBlazeOperand : public MCParsedAsmOperand {
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enum KindTy {
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Token,
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Immediate,
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Register,
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Memory,
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Fsl
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} Kind;
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SMLoc StartLoc, EndLoc;
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union {
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struct {
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const char *Data;
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unsigned Length;
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} Tok;
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struct {
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unsigned RegNum;
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} Reg;
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struct {
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const MCExpr *Val;
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} Imm;
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struct {
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unsigned Base;
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unsigned OffReg;
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const MCExpr *Off;
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} Mem;
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struct {
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const MCExpr *Val;
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} FslImm;
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};
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MBlazeOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
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public:
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MBlazeOperand(const MBlazeOperand &o) : MCParsedAsmOperand() {
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Kind = o.Kind;
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StartLoc = o.StartLoc;
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EndLoc = o.EndLoc;
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switch (Kind) {
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case Register:
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Reg = o.Reg;
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break;
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case Immediate:
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Imm = o.Imm;
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break;
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case Token:
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Tok = o.Tok;
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break;
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case Memory:
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Mem = o.Mem;
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break;
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case Fsl:
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FslImm = o.FslImm;
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break;
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}
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}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const { return EndLoc; }
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unsigned getReg() const {
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNum;
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}
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const MCExpr *getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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const MCExpr *getFslImm() const {
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assert(Kind == Fsl && "Invalid access!");
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return FslImm.Val;
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}
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unsigned getMemBase() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Base;
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}
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const MCExpr* getMemOff() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Off;
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}
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unsigned getMemOffReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.OffReg;
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}
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bool isToken() const { return Kind == Token; }
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bool isImm() const { return Kind == Immediate; }
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bool isMem() const { return Kind == Memory; }
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bool isFsl() const { return Kind == Fsl; }
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bool isReg() const { return Kind == Register; }
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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// Add as immediates when possible. Null MCExpr = 0.
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if (Expr == 0)
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Inst.addOperand(MCOperand::CreateImm(0));
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else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::CreateExpr(Expr));
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}
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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}
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void addFslOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getFslImm());
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}
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void addMemOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBase()));
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unsigned RegOff = getMemOffReg();
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if (RegOff)
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Inst.addOperand(MCOperand::CreateReg(RegOff));
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else
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addExpr(Inst, getMemOff());
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}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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virtual void print(raw_ostream &OS) const;
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static MBlazeOperand *CreateToken(StringRef Str, SMLoc S) {
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MBlazeOperand *Op = new MBlazeOperand(Token);
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Op->Tok.Data = Str.data();
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Op->Tok.Length = Str.size();
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
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MBlazeOperand *Op = new MBlazeOperand(Register);
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Op->Reg.RegNum = RegNum;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static MBlazeOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
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MBlazeOperand *Op = new MBlazeOperand(Immediate);
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Op->Imm.Val = Val;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static MBlazeOperand *CreateFslImm(const MCExpr *Val, SMLoc S, SMLoc E) {
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MBlazeOperand *Op = new MBlazeOperand(Fsl);
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Op->Imm.Val = Val;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static MBlazeOperand *CreateMem(unsigned Base, const MCExpr *Off, SMLoc S,
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SMLoc E) {
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MBlazeOperand *Op = new MBlazeOperand(Memory);
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Op->Mem.Base = Base;
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Op->Mem.Off = Off;
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Op->Mem.OffReg = 0;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static MBlazeOperand *CreateMem(unsigned Base, unsigned Off, SMLoc S,
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SMLoc E) {
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MBlazeOperand *Op = new MBlazeOperand(Memory);
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Op->Mem.Base = Base;
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Op->Mem.OffReg = Off;
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Op->Mem.Off = 0;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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};
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} // end anonymous namespace.
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void MBlazeOperand::print(raw_ostream &OS) const {
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switch (Kind) {
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case Immediate:
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getImm()->print(OS);
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break;
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case Register:
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OS << "<register R";
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OS << getMBlazeRegisterNumbering(getReg()) << ">";
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break;
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case Token:
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OS << "'" << getToken() << "'";
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break;
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case Memory: {
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OS << "<memory R";
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OS << getMBlazeRegisterNumbering(getMemBase());
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OS << ", ";
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unsigned RegOff = getMemOffReg();
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if (RegOff)
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OS << "R" << getMBlazeRegisterNumbering(RegOff);
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else
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OS << getMemOff();
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OS << ">";
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}
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break;
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case Fsl:
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getFslImm()->print(OS);
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break;
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}
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}
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/// @name Auto-generated Match Functions
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/// {
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static unsigned MatchRegisterName(StringRef Name);
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/// }
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//
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bool MBlazeAsmParser::
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MatchAndEmitInstruction(SMLoc IDLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out) {
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MCInst Inst;
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SMLoc ErrorLoc;
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unsigned ErrorInfo;
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switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
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default: break;
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case Match_Success:
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Out.EmitInstruction(Inst);
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return false;
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case Match_MissingFeature:
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return Error(IDLoc, "instruction use requires an option to be enabled");
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case Match_MnemonicFail:
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return Error(IDLoc, "unrecognized instruction mnemonic");
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case Match_ConversionFail:
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return Error(IDLoc, "unable to convert operands to instruction");
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case Match_InvalidOperand:
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ErrorLoc = IDLoc;
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if (ErrorInfo != ~0U) {
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if (ErrorInfo >= Operands.size())
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return Error(IDLoc, "too few operands for instruction");
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ErrorLoc = ((MBlazeOperand*)Operands[ErrorInfo])->getStartLoc();
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if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
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}
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return Error(ErrorLoc, "invalid operand for instruction");
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}
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llvm_unreachable("Implement any new match types added!");
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}
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MBlazeOperand *MBlazeAsmParser::
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ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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if (Operands.size() != 4)
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return 0;
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MBlazeOperand &Base = *(MBlazeOperand*)Operands[2];
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MBlazeOperand &Offset = *(MBlazeOperand*)Operands[3];
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SMLoc S = Base.getStartLoc();
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SMLoc O = Offset.getStartLoc();
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SMLoc E = Offset.getEndLoc();
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if (!Base.isReg()) {
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Error(S, "base address must be a register");
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return 0;
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}
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if (!Offset.isReg() && !Offset.isImm()) {
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Error(O, "offset must be a register or immediate");
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return 0;
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}
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MBlazeOperand *Op;
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if (Offset.isReg())
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Op = MBlazeOperand::CreateMem(Base.getReg(), Offset.getReg(), S, E);
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else
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Op = MBlazeOperand::CreateMem(Base.getReg(), Offset.getImm(), S, E);
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delete Operands.pop_back_val();
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delete Operands.pop_back_val();
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Operands.push_back(Op);
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return Op;
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}
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bool MBlazeAsmParser::ParseRegister(unsigned &RegNo,
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SMLoc &StartLoc, SMLoc &EndLoc) {
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return (ParseRegister(RegNo) == 0);
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}
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MBlazeOperand *MBlazeAsmParser::ParseRegister(unsigned &RegNo) {
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SMLoc S = Parser.getTok().getLoc();
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SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
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switch (getLexer().getKind()) {
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default: return 0;
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case AsmToken::Identifier:
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RegNo = MatchRegisterName(getLexer().getTok().getIdentifier());
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if (RegNo == 0)
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return 0;
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getLexer().Lex();
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return MBlazeOperand::CreateReg(RegNo, S, E);
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}
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}
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static unsigned MatchFslRegister(StringRef String) {
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if (!String.startswith("rfsl"))
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return -1;
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unsigned regNum;
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if (String.substr(4).getAsInteger(10,regNum))
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return -1;
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return regNum;
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}
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MBlazeOperand *MBlazeAsmParser::ParseFsl() {
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SMLoc S = Parser.getTok().getLoc();
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SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
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switch (getLexer().getKind()) {
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default: return 0;
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case AsmToken::Identifier:
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unsigned reg = MatchFslRegister(getLexer().getTok().getIdentifier());
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if (reg >= 16)
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return 0;
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getLexer().Lex();
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const MCExpr *EVal = MCConstantExpr::Create(reg,getContext());
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return MBlazeOperand::CreateFslImm(EVal,S,E);
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}
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}
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MBlazeOperand *MBlazeAsmParser::ParseImmediate() {
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SMLoc S = Parser.getTok().getLoc();
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SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
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const MCExpr *EVal;
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switch (getLexer().getKind()) {
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default: return 0;
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case AsmToken::LParen:
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case AsmToken::Plus:
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case AsmToken::Minus:
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case AsmToken::Integer:
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case AsmToken::Identifier:
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if (getParser().ParseExpression(EVal))
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return 0;
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return MBlazeOperand::CreateImm(EVal, S, E);
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}
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}
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MBlazeOperand *MBlazeAsmParser::
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ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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MBlazeOperand *Op;
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// Attempt to parse the next token as a register name
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unsigned RegNo;
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Op = ParseRegister(RegNo);
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// Attempt to parse the next token as an FSL immediate
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if (!Op)
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Op = ParseFsl();
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// Attempt to parse the next token as an immediate
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if (!Op)
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Op = ParseImmediate();
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// If the token could not be parsed then fail
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if (!Op) {
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Error(Parser.getTok().getLoc(), "unknown operand");
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return 0;
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}
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// Push the parsed operand into the list of operands
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Operands.push_back(Op);
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return Op;
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}
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/// Parse an mblaze instruction mnemonic followed by its operands.
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bool MBlazeAsmParser::
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ParseInstruction(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// The first operands is the token for the instruction name
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size_t dotLoc = Name.find('.');
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Operands.push_back(MBlazeOperand::CreateToken(Name.substr(0,dotLoc),NameLoc));
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if (dotLoc < Name.size())
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Operands.push_back(MBlazeOperand::CreateToken(Name.substr(dotLoc),NameLoc));
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// If there are no more operands then finish
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if (getLexer().is(AsmToken::EndOfStatement))
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return false;
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// Parse the first operand
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if (!ParseOperand(Operands))
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return true;
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while (getLexer().isNot(AsmToken::EndOfStatement) &&
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getLexer().is(AsmToken::Comma)) {
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// Consume the comma token
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getLexer().Lex();
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// Parse the next operand
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if (!ParseOperand(Operands))
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return true;
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}
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// If the instruction requires a memory operand then we need to
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// replace the last two operands (base+offset) with a single
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// memory operand.
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if (Name.startswith("lw") || Name.startswith("sw") ||
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Name.startswith("lh") || Name.startswith("sh") ||
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Name.startswith("lb") || Name.startswith("sb"))
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return (ParseMemory(Operands) == NULL);
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return false;
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}
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/// ParseDirective parses the MBlaze specific directives
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bool MBlazeAsmParser::ParseDirective(AsmToken DirectiveID) {
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StringRef IDVal = DirectiveID.getIdentifier();
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if (IDVal == ".word")
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return ParseDirectiveWord(2, DirectiveID.getLoc());
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return true;
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}
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/// ParseDirectiveWord
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/// ::= .word [ expression (, expression)* ]
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bool MBlazeAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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for (;;) {
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const MCExpr *Value;
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|
if (getParser().ParseExpression(Value))
|
|
return true;
|
|
|
|
getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
|
|
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
break;
|
|
|
|
// FIXME: Improve diagnostic.
|
|
if (getLexer().isNot(AsmToken::Comma))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
}
|
|
}
|
|
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
extern "C" void LLVMInitializeMBlazeAsmLexer();
|
|
|
|
/// Force static initialization.
|
|
extern "C" void LLVMInitializeMBlazeAsmParser() {
|
|
RegisterMCAsmParser<MBlazeAsmParser> X(TheMBlazeTarget);
|
|
LLVMInitializeMBlazeAsmLexer();
|
|
}
|
|
|
|
#define GET_REGISTER_MATCHER
|
|
#define GET_MATCHER_IMPLEMENTATION
|
|
#include "MBlazeGenAsmMatcher.inc"
|