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The logic is almost there already, with our special homogeneous aggregate handling. Tweaking it like this allows front-ends to emit AAPCS compliant code without ever having to count registers or add discarded padding arguments. Only arrays of i32 and i64 are needed to model AAPCS rules, but I decided to apply the logic to all integer arrays for more consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230348 91177308-0d34-0410-b5e6-96231b3b80d8
102 lines
3.4 KiB
LLVM
102 lines
3.4 KiB
LLVM
; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s
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; [2 x i64] should be contiguous when split (e.g. we shouldn't try to align all
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; i32 components to 64 bits). Also makes sure i64 based types are properly
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; aligned on the stack.
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define i64 @test_i64_contiguous_on_stack([8 x double], float, i32 %in, [2 x i64] %arg) nounwind {
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; CHECK-LABEL: test_i64_contiguous_on_stack:
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; CHECK-DAG: ldr [[LO0:r[0-9]+]], [sp, #8]
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; CHECK-DAG: ldr [[HI0:r[0-9]+]], [sp, #12]
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; CHECK-DAG: ldr [[LO1:r[0-9]+]], [sp, #16]
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; CHECK-DAG: ldr [[HI1:r[0-9]+]], [sp, #20]
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; CHECK: adds r0, [[LO0]], [[LO1]]
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; CHECK: adc r1, [[HI0]], [[HI1]]
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%val1 = extractvalue [2 x i64] %arg, 0
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%val2 = extractvalue [2 x i64] %arg, 1
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%sum = add i64 %val1, %val2
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ret i64 %sum
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}
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; [2 x i64] should try to use looks for 4 regs, not 8 (which might happen if the
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; i64 -> i32, i32 split wasn't handled correctly).
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define i64 @test_2xi64_uses_4_regs([8 x double], float, [2 x i64] %arg) nounwind {
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; CHECK-LABEL: test_2xi64_uses_4_regs:
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; CHECK-DAG: mov r0, r2
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; CHECK-DAG: mov r1, r3
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%val = extractvalue [2 x i64] %arg, 1
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ret i64 %val
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}
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; An aggregate should be able to split between registers and stack if there is
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; nothing else on the stack.
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define i32 @test_aggregates_split([8 x double], i32, [4 x i32] %arg) nounwind {
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; CHECK-LABEL: test_aggregates_split:
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; CHECK: ldr [[VAL3:r[0-9]+]], [sp]
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; CHECK: add r0, r1, [[VAL3]]
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%val0 = extractvalue [4 x i32] %arg, 0
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%val3 = extractvalue [4 x i32] %arg, 3
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%sum = add i32 %val0, %val3
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ret i32 %sum
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}
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; If an aggregate has to be moved entirely onto the stack, nothing should be
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; able to use r0-r3 any more. Also checks that [2 x i64] properly aligned when
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; it uses regs.
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define i32 @test_no_int_backfilling([8 x double], float, i32, [2 x i64], i32 %arg) nounwind {
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; CHECK-LABEL: test_no_int_backfilling:
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; CHECK: ldr r0, [sp, #24]
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ret i32 %arg
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}
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; Even if the argument was successfully allocated as reg block, there should be
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; no backfillig to r1.
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define i32 @test_no_int_backfilling_regsonly(i32, [1 x i64], i32 %arg) {
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; CHECK-LABEL: test_no_int_backfilling_regsonly:
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; CHECK: ldr r0, [sp]
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ret i32 %arg
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}
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; If an aggregate has to be moved entirely onto the stack, nothing should be
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; able to use r0-r3 any more.
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define float @test_no_float_backfilling([7 x double], [4 x i32], i32, [4 x double], float %arg) nounwind {
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; CHECK-LABEL: test_no_float_backfilling:
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; CHECK: vldr s0, [sp, #40]
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ret float %arg
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}
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; They're a bit pointless, but types like [N x i8] should work as well.
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define i8 @test_i8_in_regs(i32, [3 x i8] %arg) {
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; CHECK-LABEL: test_i8_in_regs:
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; CHECK: add r0, r1, r3
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%val0 = extractvalue [3 x i8] %arg, 0
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%val2 = extractvalue [3 x i8] %arg, 2
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%sum = add i8 %val0, %val2
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ret i8 %sum
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}
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define i16 @test_i16_split(i32, i32, [3 x i16] %arg) {
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; CHECK-LABEL: test_i16_split:
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; CHECK: ldrh [[VAL2:r[0-9]+]], [sp]
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; CHECK: add r0, r2, [[VAL2]]
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%val0 = extractvalue [3 x i16] %arg, 0
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%val2 = extractvalue [3 x i16] %arg, 2
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%sum = add i16 %val0, %val2
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ret i16 %sum
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}
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; Beware: on the stack each i16 still gets a 32-bit slot, the array is not
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; packed.
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define i16 @test_i16_forced_stack([8 x double], double, i32, i32, [3 x i16] %arg) {
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; CHECK-LABEL: test_i16_forced_stack:
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; CHECK-DAG: ldrh [[VAL0:r[0-9]+]], [sp, #8]
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; CHECK-DAG: ldrh [[VAL2:r[0-9]+]], [sp, #16]
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; CHECK: add r0, [[VAL0]], [[VAL2]]
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%val0 = extractvalue [3 x i16] %arg, 0
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%val2 = extractvalue [3 x i16] %arg, 2
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%sum = add i16 %val0, %val2
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ret i16 %sum
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}
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