llvm-6502/test/CodeGen
Rafael Espindola 2cc9ba0125 Convert test to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199355 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 06:31:20 +00:00
..
AArch64 For AArch64, lowering sext_inreg and generate optimized code by using SXTL. 2014-01-15 05:08:01 +00:00
ARM PR 18466: Fix ARM Pseudo Expansion 2014-01-15 01:32:12 +00:00
CPP
Generic
Hexagon
Inputs
Mips Adjust offsets for max load instruction offsets. This is more pessimistic 2014-01-16 00:47:46 +00:00
MSP430
NVPTX Fix non-deterministic SDNodeOrder-dependent codegen 2014-01-12 14:09:17 +00:00
PowerPC
R600 Fix broken CHECK lines. 2014-01-11 21:06:00 +00:00
SPARC Always let value types influence register classes. 2014-01-14 06:18:38 +00:00
SystemZ [SystemZ] Flesh out stackrestore test (frame-11.ll) 2014-01-13 15:44:44 +00:00
Thumb Fix broken CHECK lines. 2014-01-11 21:06:00 +00:00
Thumb2 Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks 2014-01-13 18:47:54 +00:00
X86 Convert test to FileCheck. 2014-01-16 06:31:20 +00:00
XCore Fix broken CHECK lines. 2014-01-11 21:06:00 +00:00