mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1c3af779fc
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
688 B
LLVM
39 lines
688 B
LLVM
; RUN: llc < %s -march=arm | FileCheck %s
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define i64 @f1(i64 %a, i64 %b) {
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; CHECK: f1:
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; CHECK: subs r
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; CHECK: sbc r
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entry:
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%tmp = sub i64 %a, %b
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ret i64 %tmp
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}
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define i64 @f2(i64 %a, i64 %b) {
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; CHECK: f2:
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; CHECK: adc r
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; CHECK: subs r
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; CHECK: sbc r
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entry:
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%tmp1 = shl i64 %a, 1
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%tmp2 = sub i64 %tmp1, %b
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ret i64 %tmp2
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}
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; add with live carry
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define i64 @f3(i32 %al, i32 %bl) {
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; CHECK: f3:
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; CHECK: adds r
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; CHECK: adcs r
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; CHECK: adc r
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entry:
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; unsigned wide add
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%aw = zext i32 %al to i64
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%bw = zext i32 %bl to i64
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%cw = add i64 %aw, %bw
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; ch == carry bit
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%ch = lshr i64 %cw, 32
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%dw = add i64 %ch, %bw
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ret i64 %dw
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}
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