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af73dfe6f1
The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197532 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| git | ||
| git-svn | ||
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| KillTheDoctor | ||
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| lit | ||
| llvm-build | ||
| llvm-lit | ||
| Misc | ||
| not | ||
| PerfectShuffle | ||
| release | ||
| TableGen | ||
| Target/ARM | ||
| testgen | ||
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| clang-parse-diagnostics-file | ||
| codegen-diff | ||
| countloc.sh | ||
| DSAclean.py | ||
| DSAextract.py | ||
| findmisopt | ||
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| findsym.pl | ||
| GenLibDeps.pl | ||
| GetRepositoryPath | ||
| GetSourceVersion | ||
| getsrcs.sh | ||
| lldbDataFormatters.py | ||
| llvm-compilers-check | ||
| llvm-native-gcc | ||
| llvm-native-gxx | ||
| llvm.grm | ||
| llvm.natvis | ||
| LLVMBuild.txt | ||
| llvmdo | ||
| llvmgrep | ||
| Makefile | ||
| makellvm | ||
| sort_includes.py | ||
| test_debuginfo.pl | ||
| UpdateCMakeLists.pl | ||
| wciia.py | ||