llvm-6502/test/CodeGen
Ahmed Bougacha cd5bbd8bad [X86] Also create+widen FMIN/FMAX nodes for v2f32.
This happens in the HINT benchmark, where the SLP-vectorizer created
v2f32 fcmp/select code.  The "correct" solution would have been to
teach the vectorizer cost model that v2f32 isn't legal (because really,
it isn't), but if we can vectorize we might as well do so.

We legalize these v2f32 FMIN/FMAX nodes by widening to v4f32 later on.
v3f32 were already widened to v4f32 by the generic unroll-and-build-vector
legalization.

rdar://15763436
Differential Revision: http://reviews.llvm.org/D6557


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225691 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-12 20:31:30 +00:00
..
AArch64 Fix PR22179. 2015-01-10 23:41:24 +00:00
ARM
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC [PowerPC] Fix calls to non-function objects 2015-01-12 04:34:47 +00:00
R600 R600/SI: Use RegisterOperands to specify which operands can accept immediates 2015-01-12 19:33:18 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86 [X86] Also create+widen FMIN/FMAX nodes for v2f32. 2015-01-12 20:31:30 +00:00
XCore