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c19bd32136
Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.9 KiB
ArmAsm
54 lines
1.9 KiB
ArmAsm
@ RUN: not llvm-mc -triple=thumbv7-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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@ Ill-formed IT block instructions.
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itet eq
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addle r0, r1, r2
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nop
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it le
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iteeee gt
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ittfe le
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nopeq
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@ CHECK-ERRORS: error: incorrect condition in IT block; got 'le', but expected 'eq'
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@ CHECK-ERRORS: addle r0, r1, r2
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: incorrect condition in IT block; got 'al', but expected 'ne'
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@ CHECK-ERRORS: nop
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instructions in IT block must be predicable
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@ CHECK-ERRORS: it le
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: too many conditions on IT instruction
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@ CHECK-ERRORS: iteeee gt
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: illegal IT block condition mask 'tfe'
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@ CHECK-ERRORS: ittfe le
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: predicated instructions must be in IT block
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@ CHECK-ERRORS: nopeq
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@ CHECK-ERRORS: ^
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@ Out of range immediates for MRC/MRC2/MRRC/MRRC2
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mrc p14, #8, r1, c1, c2, #4
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mrc p14, #1, r1, c1, c2, #8
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mrc2 p14, #8, r1, c1, c2, #4
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mrc2 p14, #0, r1, c1, c2, #9
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mrrc p7, #16, r5, r4, c1
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mrrc2 p7, #17, r5, r4, c1
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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isb #-1
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isb #16
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: error: immediate value out of range
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itt eq
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bkpteq #1
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@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
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