mirror of
https://github.com/c64scene-ar/llvm-6502.git
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9e67db4af1
This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154816 91177308-0d34-0410-b5e6-96231b3b80d8
176 lines
7.1 KiB
LLVM
176 lines
7.1 KiB
LLVM
; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true | FileCheck %s
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; Currently, floating-point selects are lowered to CFG triangles.
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; This means that one side of the select is always unconditionally
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; evaluated, however with MachineSink we can sink the other side so
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; that it's conditionally evaluated.
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; CHECK: foo:
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; CHECK-NEXT: testb $1, %dil
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; CHECK-NEXT: jne
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; CHECK-NEXT: divsd
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; CHECK-NEXT: movaps
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; CHECK-NEXT: ret
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; CHECK: divsd
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define double @foo(double %x, double %y, i1 %c) nounwind {
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%a = fdiv double %x, 3.2
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%b = fdiv double %y, 3.3
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%z = select i1 %c, double %a, double %b
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ret double %z
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}
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; Make sure the critical edge is broken so the divsd is sunken below
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; the conditional branch.
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; rdar://8454886
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; CHECK: split:
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; CHECK-NEXT: testb $1, %dil
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; CHECK-NEXT: jne
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; CHECK-NEXT: movaps
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; CHECK-NEXT: ret
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; CHECK: divsd
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; CHECK-NEXT: ret
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define double @split(double %x, double %y, i1 %c) nounwind {
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%a = fdiv double %x, 3.2
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%z = select i1 %c, double %a, double %y
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ret double %z
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}
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; Hoist floating-point constant-pool loads out of loops.
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; CHECK: bar:
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; CHECK: movsd
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; CHECK: align
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define void @bar(double* nocapture %p, i64 %n) nounwind {
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entry:
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%0 = icmp sgt i64 %n, 0
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br i1 %0, label %bb, label %return
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bb:
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%i.03 = phi i64 [ 0, %entry ], [ %3, %bb ]
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%scevgep = getelementptr double* %p, i64 %i.03
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%1 = load double* %scevgep, align 8
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%2 = fdiv double 3.200000e+00, %1
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store double %2, double* %scevgep, align 8
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%3 = add nsw i64 %i.03, 1
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%exitcond = icmp eq i64 %3, %n
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br i1 %exitcond, label %return, label %bb
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return:
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ret void
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}
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; Sink instructions with dead EFLAGS defs.
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; FIXME: Unfail the zzz test if we can correctly mark pregs with the kill flag.
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;
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; See <rdar://problem/8030636>. This test isn't valid after we made machine
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; sinking more conservative about sinking instructions that define a preg into a
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; block when we don't know if the preg is killed within the current block.
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; FIXMEHECK: zzz:
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; FIXMEHECK: je
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; FIXMEHECK-NEXT: orb
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; define zeroext i8 @zzz(i8 zeroext %a, i8 zeroext %b) nounwind readnone {
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; entry:
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; %tmp = zext i8 %a to i32 ; <i32> [#uses=1]
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; %tmp2 = icmp eq i8 %a, 0 ; <i1> [#uses=1]
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; %tmp3 = or i8 %b, -128 ; <i8> [#uses=1]
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; %tmp4 = and i8 %b, 127 ; <i8> [#uses=1]
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; %b_addr.0 = select i1 %tmp2, i8 %tmp4, i8 %tmp3 ; <i8> [#uses=1]
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; ret i8 %b_addr.0
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; }
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; Codegen should hoist and CSE these constants.
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; CHECK: vv:
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; CHECK: LCPI3_0(%rip), %xmm0
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; CHECK: LCPI3_1(%rip), %xmm1
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; CHECK: LCPI3_2(%rip), %xmm2
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; CHECK: align
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; CHECK-NOT: LCPI
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; CHECK: ret
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@_minusZero.6007 = internal constant <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00> ; <<4 x float>*> [#uses=0]
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@twoTo23.6008 = internal constant <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06> ; <<4 x float>*> [#uses=0]
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define void @vv(float* %y, float* %x, i32* %n) nounwind ssp {
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entry:
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br label %bb60
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bb: ; preds = %bb60
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%i.0 = phi i32 [ 0, %bb60 ] ; <i32> [#uses=2]
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%0 = bitcast float* %x_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1]
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%1 = load <4 x float>* %0, align 16 ; <<4 x float>> [#uses=4]
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%tmp20 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp22 = and <4 x i32> %tmp20, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1]
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%tmp23 = bitcast <4 x i32> %tmp22 to <4 x float> ; <<4 x float>> [#uses=1]
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%tmp25 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp27 = and <4 x i32> %tmp25, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=2]
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%tmp30 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %tmp23, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) ; <<4 x float>> [#uses=1]
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%tmp34 = bitcast <4 x float> %tmp30 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp36 = xor <4 x i32> %tmp34, <i32 -1, i32 -1, i32 -1, i32 -1> ; <<4 x i32>> [#uses=1]
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%tmp37 = and <4 x i32> %tmp36, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> ; <<4 x i32>> [#uses=1]
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%tmp42 = or <4 x i32> %tmp37, %tmp27 ; <<4 x i32>> [#uses=1]
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%tmp43 = bitcast <4 x i32> %tmp42 to <4 x float> ; <<4 x float>> [#uses=2]
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%tmp45 = fadd <4 x float> %1, %tmp43 ; <<4 x float>> [#uses=1]
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%tmp47 = fsub <4 x float> %tmp45, %tmp43 ; <<4 x float>> [#uses=2]
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%tmp49 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %1, <4 x float> %tmp47, i8 1) ; <<4 x float>> [#uses=1]
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%2 = bitcast <4 x float> %tmp49 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%3 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %2) nounwind readnone ; <<4 x float>> [#uses=1]
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%tmp53 = fadd <4 x float> %tmp47, %3 ; <<4 x float>> [#uses=1]
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%tmp55 = bitcast <4 x float> %tmp53 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp57 = or <4 x i32> %tmp55, %tmp27 ; <<4 x i32>> [#uses=1]
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%tmp58 = bitcast <4 x i32> %tmp57 to <4 x float> ; <<4 x float>> [#uses=1]
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%4 = bitcast float* %y_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1]
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store <4 x float> %tmp58, <4 x float>* %4, align 16
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%5 = getelementptr float* %x_addr.0, i64 4 ; <float*> [#uses=1]
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%6 = getelementptr float* %y_addr.0, i64 4 ; <float*> [#uses=1]
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%7 = add i32 %i.0, 4 ; <i32> [#uses=1]
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%8 = load i32* %n, align 4 ; <i32> [#uses=1]
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%9 = icmp sgt i32 %8, %7 ; <i1> [#uses=1]
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br i1 %9, label %bb60, label %return
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bb60: ; preds = %bb, %entry
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%x_addr.0 = phi float* [ %x, %entry ], [ %5, %bb ] ; <float*> [#uses=2]
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%y_addr.0 = phi float* [ %y, %entry ], [ %6, %bb ] ; <float*> [#uses=2]
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br label %bb
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return: ; preds = %bb60
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ret void
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}
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declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
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declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
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; CodeGen should use the correct register class when extracting
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; a load from a zero-extending load for hoisting.
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; CHECK: default_get_pch_validity:
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; CHECK: movl cl_options_count(%rip), %ecx
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@cl_options_count = external constant i32 ; <i32*> [#uses=2]
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define void @default_get_pch_validity() nounwind {
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entry:
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%tmp4 = load i32* @cl_options_count, align 4 ; <i32> [#uses=1]
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%tmp5 = icmp eq i32 %tmp4, 0 ; <i1> [#uses=1]
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br i1 %tmp5, label %bb6, label %bb2
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bb2: ; preds = %bb2, %entry
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%i.019 = phi i64 [ 0, %entry ], [ %tmp25, %bb2 ] ; <i64> [#uses=1]
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%tmp25 = add i64 %i.019, 1 ; <i64> [#uses=2]
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%tmp11 = load i32* @cl_options_count, align 4 ; <i32> [#uses=1]
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%tmp12 = zext i32 %tmp11 to i64 ; <i64> [#uses=1]
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%tmp13 = icmp ugt i64 %tmp12, %tmp25 ; <i1> [#uses=1]
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br i1 %tmp13, label %bb2, label %bb6
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bb6: ; preds = %bb2, %entry
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ret void
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}
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