llvm-6502/test/CodeGen
Yunzhong Gao 685707c28e Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 18:38:42 +00:00
..
AArch64 llvm/test/CodeGen/AArch64/neon-scalar-reduce-pairwise.ll: Use -mtriple here, or aach64-pecoff might be misassumed on win32 hosts. 2013-09-24 04:14:29 +00:00
ARM Fix PR 17372: Emitting PLD for stack address for ARM Thumb2 2013-09-26 17:25:10 +00:00
CPP
Generic
Hexagon
Inputs
Mips [mips][msa] Implemented insert.d intrinsic. 2013-09-27 13:36:54 +00:00
MSP430
NVPTX [NVPTX] Make constant vector test case endian-independent 2013-09-19 13:14:44 +00:00
PowerPC [PowerPC] Fix PR17354: Generate nop after local calls for PIC code. 2013-09-26 17:09:28 +00:00
R600 R600: Move code handling literal folding into R600ISelLowering. 2013-09-12 23:44:53 +00:00
SPARC [Sparc] Implements exception handling in SPARC with DwarfCFI. 2013-09-26 15:11:00 +00:00
SystemZ TBAA: handle scalar TBAA format and struct-path aware TBAA format. 2013-09-27 18:34:27 +00:00
Thumb
Thumb2 [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode. 2013-09-09 14:21:49 +00:00
X86 Adding intrinsics to the llvm backend for TBM instruction set. 2013-09-27 18:38:42 +00:00
XCore XCore handling of thread local lowering 2013-09-09 10:42:11 +00:00