mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-03 08:55:51 +00:00
184f8f7c10
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
103 lines
2.5 KiB
LLVM
103 lines
2.5 KiB
LLVM
; RUN: llc < %s -march=ppc64 | FileCheck %s
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; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s
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; RUN: llc < %s -march=ppc64 -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U
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define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
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; CHECK-LABEL: exchange_and_add:
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; CHECK: ldarx
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%tmp = atomicrmw add i64* %mem, i64 %val monotonic
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i8 @exchange_and_add8(i8* %mem, i8 %val) nounwind {
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; CHECK-LABEL: exchange_and_add8:
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; CHECK-P8U: lbarx
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%tmp = atomicrmw add i8* %mem, i8 %val monotonic
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; CHECK-P8U: stbcx.
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ret i8 %tmp
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}
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define i16 @exchange_and_add16(i16* %mem, i16 %val) nounwind {
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; CHECK-LABEL: exchange_and_add16:
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; CHECK-P8U: lharx
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%tmp = atomicrmw add i16* %mem, i16 %val monotonic
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; CHECK-P8U: sthcx.
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ret i16 %tmp
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}
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define i64 @exchange_and_cmp(i64* %mem) nounwind {
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; CHECK-LABEL: exchange_and_cmp:
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; CHECK: ldarx
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%tmppair = cmpxchg i64* %mem, i64 0, i64 1 monotonic monotonic
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%tmp = extractvalue { i64, i1 } %tmppair, 0
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; CHECK: stdcx.
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i8 @exchange_and_cmp8(i8* %mem) nounwind {
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; CHECK-LABEL: exchange_and_cmp8:
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; CHECK-P8U: lbarx
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%tmppair = cmpxchg i8* %mem, i8 0, i8 1 monotonic monotonic
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%tmp = extractvalue { i8, i1 } %tmppair, 0
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; CHECK-P8U: stbcx.
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; CHECK-P8U: stbcx.
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ret i8 %tmp
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}
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define i16 @exchange_and_cmp16(i16* %mem) nounwind {
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; CHECK-LABEL: exchange_and_cmp16:
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; CHECK-P8U: lharx
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%tmppair = cmpxchg i16* %mem, i16 0, i16 1 monotonic monotonic
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%tmp = extractvalue { i16, i1 } %tmppair, 0
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; CHECK-P8U: sthcx.
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; CHECK-P8U: sthcx.
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ret i16 %tmp
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}
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define i64 @exchange(i64* %mem, i64 %val) nounwind {
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; CHECK-LABEL: exchange:
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; CHECK: ldarx
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%tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i8 @exchange8(i8* %mem, i8 %val) nounwind {
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; CHECK-LABEL: exchange8:
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; CHECK-P8U: lbarx
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%tmp = atomicrmw xchg i8* %mem, i8 1 monotonic
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; CHECK-P8U: stbcx.
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ret i8 %tmp
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}
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define i16 @exchange16(i16* %mem, i16 %val) nounwind {
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; CHECK-LABEL: exchange16:
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; CHECK-P8U: lharx
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%tmp = atomicrmw xchg i16* %mem, i16 1 monotonic
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; CHECK-P8U: sthcx.
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ret i16 %tmp
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}
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define void @atomic_store(i64* %mem, i64 %val) nounwind {
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entry:
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; CHECK: @atomic_store
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store atomic i64 %val, i64* %mem release, align 64
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; CHECK: lwsync
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; CHECK-NOT: stdcx
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; CHECK: std
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ret void
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}
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define i64 @atomic_load(i64* %mem) nounwind {
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entry:
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; CHECK: @atomic_load
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%tmp = load atomic i64, i64* %mem acquire, align 64
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; CHECK-NOT: ldarx
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; CHECK: ld
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; CHECK: lwsync
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ret i64 %tmp
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}
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