mirror of
https://github.com/c64scene-ar/llvm-6502.git
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9ed58dff86
for integer and fp constants. Implement todo to use vfp3 instructions to materialize easy constants if we can. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113453 91177308-0d34-0410-b5e6-96231b3b80d8
748 lines
26 KiB
C++
748 lines
26 KiB
C++
//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the ARM-specific support for the FastISel class. Some
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// of the target-specific code is generated by tablegen in the file
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// ARMGenFastISel.inc, which is #included here.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMRegisterInfo.h"
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#include "ARMTargetMachine.h"
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#include "ARMSubtarget.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/Instructions.h"
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#include "llvm/IntrinsicInst.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CallSite.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/GetElementPtrTypeIterator.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::opt<bool>
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EnableARMFastISel("arm-fast-isel",
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cl::desc("Turn on experimental ARM fast-isel support"),
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cl::init(false), cl::Hidden);
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namespace {
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class ARMFastISel : public FastISel {
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const ARMSubtarget *Subtarget;
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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const ARMFunctionInfo *AFI;
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// Convenience variable to avoid checking all the time.
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bool isThumb;
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public:
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explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
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: FastISel(funcInfo),
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TM(funcInfo.MF->getTarget()),
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TII(*TM.getInstrInfo()),
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TLI(*TM.getTargetLowering()) {
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
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isThumb = AFI->isThumbFunction();
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}
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// Code from FastISel.cpp.
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virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC);
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virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill);
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virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm);
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virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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const ConstantFP *FPImm);
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virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm);
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virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm);
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virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
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unsigned Op0, bool Op0IsKill,
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uint32_t Idx);
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// Backend specific FastISel code.
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virtual bool TargetSelectInstruction(const Instruction *I);
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virtual unsigned TargetMaterializeConstant(const Constant *C);
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#include "ARMGenFastISel.inc"
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// Instruction selection routines.
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virtual bool ARMSelectLoad(const Instruction *I);
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virtual bool ARMSelectStore(const Instruction *I);
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virtual bool ARMSelectBranch(const Instruction *I);
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virtual bool ARMSelectCmp(const Instruction *I);
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// Utility routines.
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private:
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bool isTypeLegal(const Type *Ty, EVT &VT);
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bool isLoadTypeLegal(const Type *Ty, EVT &VT);
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
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bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
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bool ARMLoadAlloca(const Instruction *I, EVT VT);
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bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
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bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
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unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
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unsigned ARMMaterializeInt(const Constant *C);
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bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
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const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
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};
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} // end anonymous namespace
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// #include "ARMGenCallingConv.inc"
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// DefinesOptionalPredicate - This is different from DefinesPredicate in that
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// we don't care about implicit defs here, just places we'll need to add a
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// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
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bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.hasOptionalDef())
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return false;
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// Look to see if our OptionalDef is defining CPSR or CCR.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef()) continue;
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if (MO.getReg() == ARM::CPSR)
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*CPSR = true;
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}
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return true;
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}
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// If the machine is predicable go ahead and add the predicate operands, if
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// it needs default CC operands add those.
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const MachineInstrBuilder &
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ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
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MachineInstr *MI = &*MIB;
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// Do we use a predicate?
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if (TII.isPredicable(MI))
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AddDefaultPred(MIB);
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// Do we optionally set a predicate? Preds is size > 0 iff the predicate
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// defines CPSR. All other OptionalDefines in ARM are the CCR register.
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bool CPSR = false;
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if (DefinesOptionalPredicate(MI, &CPSR)) {
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if (CPSR)
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AddDefaultT1CC(MIB);
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else
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AddDefaultCC(MIB);
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}
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return MIB;
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}
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unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass* RC) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addImm(Imm));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addImm(Imm));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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const ConstantFP *FPImm) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addFPImm(FPImm));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addFPImm(FPImm));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill)
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.addImm(Imm));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill)
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.addImm(Imm));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addImm(Imm));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addImm(Imm));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
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unsigned Op0, bool Op0IsKill,
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uint32_t Idx) {
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
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assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
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"Cannot yet extract from physregs");
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
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DL, TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(Op0, getKillRegState(Op0IsKill), Idx));
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return ResultReg;
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}
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// For double width floating point we need to materialize two constants
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// (the high and the low) into integer registers then use a move to get
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// the combined constant into an FP reg.
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unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
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const APFloat Val = CFP->getValueAPF();
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bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
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// This checks to see if we can use VFP3 instructions to materialize
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// a constant, otherwise we have to go through the constant pool.
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if (TLI.isFPImmLegal(Val, VT)) {
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unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
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unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
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DestReg)
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.addFPImm(CFP));
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return DestReg;
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}
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// No 64-bit at the moment.
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if (is64bit) return 0;
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// Load this from the constant pool.
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unsigned DestReg = ARMMaterializeInt(cast<Constant>(CFP));
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// If we have a floating point constant we expect it in a floating point
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// register.
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unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::VMOVRS), MoveReg)
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.addReg(DestReg));
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return MoveReg;
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}
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unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
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// MachineConstantPool wants an explicit alignment.
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unsigned Align = TD.getPrefTypeAlignment(C->getType());
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if (Align == 0) {
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// TODO: Figure out if this is correct.
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Align = TD.getTypeAllocSize(C->getType());
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}
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unsigned Idx = MCP.getConstantPoolIndex(C, Align);
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unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
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if (isThumb)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::t2LDRpci))
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.addReg(DestReg).addConstantPoolIndex(Idx));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::LDRcp))
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.addReg(DestReg).addConstantPoolIndex(Idx)
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.addReg(0).addImm(0));
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return DestReg;
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}
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unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
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EVT VT = TLI.getValueType(C->getType(), true);
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// Only handle simple types.
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if (!VT.isSimple()) return 0;
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if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return ARMMaterializeFP(CFP, VT);
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return ARMMaterializeInt(C);
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}
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bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
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VT = TLI.getValueType(Ty, true);
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// Only handle simple types.
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if (VT == MVT::Other || !VT.isSimple()) return false;
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// Handle all legal types, i.e. a register that will directly hold this
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// value.
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return TLI.isTypeLegal(VT);
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}
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bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
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if (isTypeLegal(Ty, VT)) return true;
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// If this is a type than can be sign or zero-extended to a basic operation
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// go ahead and accept it now.
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if (VT == MVT::i8 || VT == MVT::i16)
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return true;
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return false;
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}
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// Computes the Reg+Offset to get to an object.
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bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
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int &Offset) {
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// Some boilerplate from the X86 FastISel.
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const User *U = NULL;
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unsigned Opcode = Instruction::UserOp1;
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if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
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// Don't walk into other basic blocks; it's possible we haven't
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// visited them yet, so the instructions may not yet be assigned
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// virtual registers.
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if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
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return false;
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Opcode = I->getOpcode();
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U = I;
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} else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
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Opcode = C->getOpcode();
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U = C;
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}
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if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
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if (Ty->getAddressSpace() > 255)
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// Fast instruction selection doesn't support the special
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// address spaces.
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return false;
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switch (Opcode) {
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default:
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//errs() << "Failing Opcode is: " << *Op1 << "\n";
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break;
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case Instruction::Alloca: {
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assert(false && "Alloca should have been handled earlier!");
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return false;
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}
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}
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if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
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//errs() << "Failing GV is: " << GV << "\n";
|
|
(void)GV;
|
|
return false;
|
|
}
|
|
|
|
// Try to get this in a register if nothing else has worked.
|
|
Reg = getRegForValue(Obj);
|
|
if (Reg == 0) return false;
|
|
|
|
// Since the offset may be too large for the load instruction
|
|
// get the reg+offset into a register.
|
|
// TODO: Verify the additions work, otherwise we'll need to add the
|
|
// offset instead of 0 to the instructions and do all sorts of operand
|
|
// munging.
|
|
// TODO: Optimize this somewhat.
|
|
if (Offset != 0) {
|
|
ARMCC::CondCodes Pred = ARMCC::AL;
|
|
unsigned PredReg = 0;
|
|
|
|
if (!isThumb)
|
|
emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
Reg, Reg, Offset, Pred, PredReg,
|
|
static_cast<const ARMBaseInstrInfo&>(TII));
|
|
else {
|
|
assert(AFI->isThumb2Function());
|
|
emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
Reg, Reg, Offset, Pred, PredReg,
|
|
static_cast<const ARMBaseInstrInfo&>(TII));
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
|
|
Value *Op0 = I->getOperand(0);
|
|
|
|
// Verify it's an alloca.
|
|
if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
|
|
DenseMap<const AllocaInst*, int>::iterator SI =
|
|
FuncInfo.StaticAllocaMap.find(AI);
|
|
|
|
if (SI != FuncInfo.StaticAllocaMap.end()) {
|
|
TargetRegisterClass* RC = TLI.getRegClassFor(VT);
|
|
unsigned ResultReg = createResultReg(RC);
|
|
TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
|
|
ResultReg, SI->second, RC,
|
|
TM.getRegisterInfo());
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
|
|
unsigned Reg, int Offset) {
|
|
|
|
assert(VT.isSimple() && "Non-simple types are invalid here!");
|
|
unsigned Opc;
|
|
|
|
switch (VT.getSimpleVT().SimpleTy) {
|
|
default:
|
|
assert(false && "Trying to emit for an unhandled type!");
|
|
return false;
|
|
case MVT::i16:
|
|
Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
|
|
VT = MVT::i32;
|
|
break;
|
|
case MVT::i8:
|
|
Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
|
|
VT = MVT::i32;
|
|
break;
|
|
case MVT::i32:
|
|
Opc = isThumb ? ARM::tLDR : ARM::LDR;
|
|
break;
|
|
}
|
|
|
|
ResultReg = createResultReg(TLI.getRegClassFor(VT));
|
|
|
|
// TODO: Fix the Addressing modes so that these can share some code.
|
|
// Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
|
|
if (isThumb)
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
TII.get(Opc), ResultReg)
|
|
.addReg(Reg).addImm(Offset).addReg(0));
|
|
else
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
TII.get(Opc), ResultReg)
|
|
.addReg(Reg).addReg(0).addImm(Offset));
|
|
|
|
return true;
|
|
}
|
|
|
|
bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
|
|
Value *Op1 = I->getOperand(1);
|
|
|
|
// Verify it's an alloca.
|
|
if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
|
|
DenseMap<const AllocaInst*, int>::iterator SI =
|
|
FuncInfo.StaticAllocaMap.find(AI);
|
|
|
|
if (SI != FuncInfo.StaticAllocaMap.end()) {
|
|
TargetRegisterClass* RC = TLI.getRegClassFor(VT);
|
|
assert(SrcReg != 0 && "Nothing to store!");
|
|
TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
|
|
SrcReg, true /*isKill*/, SI->second, RC,
|
|
TM.getRegisterInfo());
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
|
|
unsigned DstReg, int Offset) {
|
|
unsigned StrOpc;
|
|
switch (VT.getSimpleVT().SimpleTy) {
|
|
default: return false;
|
|
case MVT::i1:
|
|
case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
|
|
case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
|
|
case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
|
|
case MVT::f32:
|
|
if (!Subtarget->hasVFP2()) return false;
|
|
StrOpc = ARM::VSTRS;
|
|
break;
|
|
case MVT::f64:
|
|
if (!Subtarget->hasVFP2()) return false;
|
|
StrOpc = ARM::VSTRD;
|
|
break;
|
|
}
|
|
|
|
if (isThumb)
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
TII.get(StrOpc), SrcReg)
|
|
.addReg(DstReg).addImm(Offset).addReg(0));
|
|
else
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
TII.get(StrOpc), SrcReg)
|
|
.addReg(DstReg).addReg(0).addImm(Offset));
|
|
|
|
return true;
|
|
}
|
|
|
|
bool ARMFastISel::ARMSelectStore(const Instruction *I) {
|
|
Value *Op0 = I->getOperand(0);
|
|
unsigned SrcReg = 0;
|
|
|
|
// Yay type legalization
|
|
EVT VT;
|
|
if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
|
|
return false;
|
|
|
|
// Get the value to be stored into a register.
|
|
SrcReg = getRegForValue(Op0);
|
|
if (SrcReg == 0)
|
|
return false;
|
|
|
|
// If we're an alloca we know we have a frame index and can emit the store
|
|
// quickly.
|
|
if (ARMStoreAlloca(I, SrcReg, VT))
|
|
return true;
|
|
|
|
// Our register and offset with innocuous defaults.
|
|
unsigned Reg = 0;
|
|
int Offset = 0;
|
|
|
|
// See if we can handle this as Reg + Offset
|
|
if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
|
|
return false;
|
|
|
|
if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
|
|
// Verify we have a legal type before going any further.
|
|
EVT VT;
|
|
if (!isLoadTypeLegal(I->getType(), VT))
|
|
return false;
|
|
|
|
// If we're an alloca we know we have a frame index and can emit the load
|
|
// directly in short order.
|
|
if (ARMLoadAlloca(I, VT))
|
|
return true;
|
|
|
|
// Our register and offset with innocuous defaults.
|
|
unsigned Reg = 0;
|
|
int Offset = 0;
|
|
|
|
// See if we can handle this as Reg + Offset
|
|
if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
|
|
return false;
|
|
|
|
unsigned ResultReg;
|
|
if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
|
|
const BranchInst *BI = cast<BranchInst>(I);
|
|
MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
|
|
MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
|
|
|
|
// Simple branch support.
|
|
unsigned CondReg = getRegForValue(BI->getCondition());
|
|
if (CondReg == 0) return false;
|
|
|
|
unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
|
|
unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
|
|
.addReg(CondReg).addReg(CondReg));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
|
|
.addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
|
|
FastEmitBranch(FBB, DL);
|
|
FuncInfo.MBB->addSuccessor(TBB);
|
|
return true;
|
|
}
|
|
|
|
bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
|
|
const CmpInst *CI = cast<CmpInst>(I);
|
|
|
|
EVT VT;
|
|
const Type *Ty = CI->getOperand(0)->getType();
|
|
if (!isTypeLegal(Ty, VT))
|
|
return false;
|
|
|
|
bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
|
|
if (isFloat && !Subtarget->hasVFP2())
|
|
return false;
|
|
|
|
unsigned CmpOpc;
|
|
switch (VT.getSimpleVT().SimpleTy) {
|
|
default: return false;
|
|
// TODO: Verify compares.
|
|
case MVT::f32:
|
|
CmpOpc = ARM::VCMPES;
|
|
break;
|
|
case MVT::f64:
|
|
CmpOpc = ARM::VCMPED;
|
|
break;
|
|
case MVT::i32:
|
|
CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
|
|
break;
|
|
}
|
|
|
|
unsigned Arg1 = getRegForValue(CI->getOperand(0));
|
|
if (Arg1 == 0) return false;
|
|
|
|
unsigned Arg2 = getRegForValue(CI->getOperand(1));
|
|
if (Arg2 == 0) return false;
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
|
|
.addReg(Arg1).addReg(Arg2));
|
|
|
|
// For floating point we need to move the result to a register we can
|
|
// actually do something with.
|
|
if (isFloat)
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
TII.get(ARM::FMSTAT)));
|
|
return true;
|
|
}
|
|
|
|
// TODO: SoftFP support.
|
|
bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
|
|
// No Thumb-1 for now.
|
|
if (isThumb && !AFI->isThumb2Function()) return false;
|
|
|
|
switch (I->getOpcode()) {
|
|
case Instruction::Load:
|
|
return ARMSelectLoad(I);
|
|
case Instruction::Store:
|
|
return ARMSelectStore(I);
|
|
case Instruction::Br:
|
|
return ARMSelectBranch(I);
|
|
case Instruction::ICmp:
|
|
case Instruction::FCmp:
|
|
return ARMSelectCmp(I);
|
|
default: break;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
namespace llvm {
|
|
llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
|
|
if (EnableARMFastISel) return new ARMFastISel(funcInfo);
|
|
return 0;
|
|
}
|
|
}
|