mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 19:30:10 +00:00
f57b845547
- Rename runOnMethod to runOnFunction
* Transform getAnalysisUsageInfo into getAnalysisUsage
- Method is now const
- It now takes one AnalysisUsage object to fill in instead of 3 vectors
to fill in
- Pass's now specify which other passes they _preserve_ not which ones
they modify (be conservative!)
- A pass can specify that it preserves all analyses (because it never
modifies the underlying program)
* s/Method/Function/g in other random places as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2333 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
1.4 KiB
C++
40 lines
1.4 KiB
C++
//===-- InstrScheduling.h - Interface To Instruction Scheduling --*- C++ -*-==//
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//
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// This file defines a minimal, but complete, interface to instruction
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// scheduling.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
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#define LLVM_CODEGEN_INSTR_SCHEDULING_H
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class Pass;
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class TargetMachine;
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//---------------------------------------------------------------------------
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// Function: createScheduleInstructionsWithSSAPass(..)
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//
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// Purpose:
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// Entry point for instruction scheduling on SSA form.
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// Schedules the machine instructions generated by instruction selection.
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// Assumes that register allocation has not been done, i.e., operands
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// are still in SSA form.
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//---------------------------------------------------------------------------
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Pass *createInstructionSchedulingWithSSAPass(const TargetMachine &Target);
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//---------------------------------------------------------------------------
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// Function: ScheduleInstructions
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//
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// Purpose:
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// Entry point for instruction scheduling on machine code.
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// Schedules the machine instructions generated by instruction selection.
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// Assumes that register allocation has been done.
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//---------------------------------------------------------------------------
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// Not implemented yet.
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//bool ScheduleInstructions(Method *M, const TargetMachine &Target);
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#endif
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