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https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
2.0 KiB
LLVM
59 lines
2.0 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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; Vararg saving must save Q registers using the equivalent of STR/STP.
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target datalayout = "E-m:e-i64:64-i128:128-n32:64-S128"
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target triple = "arm64_be-arm-none-eabi"
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%struct.__va_list = type { i8*, i8*, i8*, i32, i32 }
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declare void @llvm.va_start(i8*) nounwind
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declare void @llvm.va_end(i8*) nounwind
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define double @callee(i32 %a, ...) {
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; CHECK: stp
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; CHECK: stp
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; CHECK: stp
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; CHECK: stp
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; CHECK: stp
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; CHECK: stp
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entry:
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%vl = alloca %struct.__va_list, align 8
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%vl1 = bitcast %struct.__va_list* %vl to i8*
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call void @llvm.va_start(i8* %vl1)
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%vr_offs_p = getelementptr inbounds %struct.__va_list* %vl, i64 0, i32 4
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%vr_offs = load i32* %vr_offs_p, align 4
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%0 = icmp sgt i32 %vr_offs, -1
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br i1 %0, label %vaarg.on_stack, label %vaarg.maybe_reg
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vaarg.maybe_reg: ; preds = %entry
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%new_reg_offs = add i32 %vr_offs, 16
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store i32 %new_reg_offs, i32* %vr_offs_p, align 4
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%inreg = icmp slt i32 %new_reg_offs, 1
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br i1 %inreg, label %vaarg.in_reg, label %vaarg.on_stack
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vaarg.in_reg: ; preds = %vaarg.maybe_reg
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%reg_top_p = getelementptr inbounds %struct.__va_list* %vl, i64 0, i32 2
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%reg_top = load i8** %reg_top_p, align 8
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%1 = sext i32 %vr_offs to i64
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%2 = getelementptr i8* %reg_top, i64 %1
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%3 = ptrtoint i8* %2 to i64
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%align_be = add i64 %3, 8
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%4 = inttoptr i64 %align_be to i8*
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br label %vaarg.end
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vaarg.on_stack: ; preds = %vaarg.maybe_reg, %entry
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%stack_p = getelementptr inbounds %struct.__va_list* %vl, i64 0, i32 0
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%stack = load i8** %stack_p, align 8
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%new_stack = getelementptr i8* %stack, i64 8
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store i8* %new_stack, i8** %stack_p, align 8
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br label %vaarg.end
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vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg
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%.sink = phi i8* [ %4, %vaarg.in_reg ], [ %stack, %vaarg.on_stack ]
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%5 = bitcast i8* %.sink to double*
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%6 = load double* %5, align 8
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call void @llvm.va_end(i8* %vl1)
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ret double %6
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}
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