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d24ba9ff6e
As Andy pointed out to me a long time ago, there are no structural hazards in the later pipeline stages of the A2, and so modeling them is useless. Also, modeling the top pre-dispatch stages is deceiving because, when multiple hardware threads are active, those resources are shared among the threads. The bypass definitions were mostly wrong, and so those have been removed. The resulting itinerary is much simpler, and more accurate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190562 91177308-0d34-0410-b5e6-96231b3b80d8
311 lines
18 KiB
TableGen
311 lines
18 KiB
TableGen
//===-- PPCScheduleE500mc.td - e5500 Scheduling Defs -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the Freescale e5500 64-bit
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// Power processor.
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//
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// All information is derived from the "e5500 Core Reference Manual",
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// Freescale Document Number e5500RM, Rev. 1, 03/2012.
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//
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//===----------------------------------------------------------------------===//
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// Relevant functional units in the Freescale e5500 core
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// (These are the same as for the e500mc)
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//
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// * Decode & Dispatch
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// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
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// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
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// def DIS0 : FuncUnit;
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// def DIS1 : FuncUnit;
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// * Execute
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// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
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// The CFX has a bypass path, allowing non-divide instructions to execute
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// while a divide instruction is being executed.
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// def SFX0 : FuncUnit; // Simple unit 0
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// def SFX1 : FuncUnit; // Simple unit 1
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// def BU : FuncUnit; // Branch unit
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// def CFX_DivBypass
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// : FuncUnit; // CFX divide bypass path
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// def CFX_0 : FuncUnit; // CFX pipeline stage 0
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def CFX_1 : FuncUnit; // CFX pipeline stage 1
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// def LSU_0 : FuncUnit; // LSU pipeline
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// def FPU_0 : FuncUnit; // FPU pipeline
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// def CR_Bypass : Bypass;
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def PPCE5500Itineraries : ProcessorItineraries<
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[DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, CFX_1,
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LSU_0, FPU_0],
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[CR_Bypass, GPR_Bypass, FPR_Bypass], [
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InstrItinData<IntSimple , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[5, 2, 2], // Latency = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntGeneral , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[5, 2, 2], // Latency = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntCompare , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[6, 2, 2], // Latency = 1 or 2
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[CR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntDivD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0], 0>,
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InstrStage<26, [CFX_DivBypass]>],
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[30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntDivW , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0], 0>,
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InstrStage<16, [CFX_DivBypass]>],
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[20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMFFS , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [FPU_0]>],
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[11], // Latency = 7, Repeat rate = 1
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[FPR_Bypass]>,
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InstrItinData<IntMTFSB0 , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<7, [FPU_0]>],
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[11, 2, 2], // Latency = 7, Repeat rate = 7
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[NoBypass, NoBypass, NoBypass]>,
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InstrItinData<IntMulHD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0], 0>,
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InstrStage<2, [CFX_1]>],
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[9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulHW , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0], 0>,
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InstrStage<1, [CFX_1]>],
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[8, 2, 2], // Latency = 4, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulHWU , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0], 0>,
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InstrStage<1, [CFX_1]>],
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[8, 2, 2], // Latency = 4, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulLI , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0], 0>,
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InstrStage<2, [CFX_1]>],
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[8, 2, 2], // Latency = 4 or 5, Repeat = 2
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntRotate , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[5, 2, 2], // Latency = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntRotateD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<2, [SFX0, SFX1]>],
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[6, 2, 2], // Latency = 2, Repeat rate = 2
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntRotateDI , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[5, 2, 2], // Latency = 1, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntShift , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<2, [SFX0, SFX1]>],
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[6, 2, 2], // Latency = 2, Repeat rate = 2
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntTrapW , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<2, [SFX0]>],
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[6, 2], // Latency = 2, Repeat rate = 2
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<BrB , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [BU]>],
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[5, 2], // Latency = 1
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[NoBypass, GPR_Bypass]>,
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InstrItinData<BrCR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [BU]>],
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[5, 2, 2], // Latency = 1
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[CR_Bypass, CR_Bypass, CR_Bypass]>,
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InstrItinData<BrMCR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [BU]>],
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[5, 2], // Latency = 1
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[CR_Bypass, CR_Bypass]>,
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InstrItinData<BrMCRX , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0]>],
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[5, 2, 2], // Latency = 1
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[CR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStDCBA , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStDCBF , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStDCBI , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLoad , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLoadUpd , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStLD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLDARX , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<3, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 3
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLDU , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStStore , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStStoreUpd, [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[NoBypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStICBI , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStSTFD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2, 2], // Latency = 3, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStSTFDU , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2, 2], // Latency = 3, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStLFD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[8, 2, 2], // Latency = 4, Repeat rate = 1
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[FPR_Bypass, GPR_Bypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStLFDU , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[8, 2, 2], // Latency = 4, Repeat rate = 1
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[FPR_Bypass, GPR_Bypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStLHA , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLHAU , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStLMW , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<4, [LSU_0]>],
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[8, 2], // Latency = r+3, Repeat rate = r+3
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStLWARX , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<3, [LSU_0]>],
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[7, 2, 2], // Latency = 3, Repeat rate = 3
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStSTD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStSTDCX , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStSTDU , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[NoBypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStSTWCX , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 2], // Latency = 3, Repeat rate = 1
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStSync , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>]>,
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InstrItinData<SprMTMSR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<2, [CFX_0]>],
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[6, 2], // Latency = 2, Repeat rate = 4
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<SprTLBSYNC , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0], 0>]>,
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InstrItinData<SprMFCR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<5, [CFX_0]>],
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[9, 2], // Latency = 5, Repeat rate = 5
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[GPR_Bypass, CR_Bypass]>,
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InstrItinData<SprMFMSR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<4, [SFX0]>],
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[8, 2], // Latency = 4, Repeat rate = 4
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<SprMFSPR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0]>],
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[5], // Latency = 1, Repeat rate = 1
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[GPR_Bypass]>,
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InstrItinData<SprMFTB , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<4, [CFX_0]>],
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[8, 2], // Latency = 4, Repeat rate = 4
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[NoBypass, GPR_Bypass]>,
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InstrItinData<SprMTSPR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[5], // Latency = 1, Repeat rate = 1
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[GPR_Bypass]>,
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InstrItinData<FPGeneral , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [FPU_0]>],
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[11, 2, 2], // Latency = 7, Repeat rate = 1
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[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPAddSub , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [FPU_0]>],
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[11, 2, 2], // Latency = 7, Repeat rate = 1
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[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPCompare , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [FPU_0]>],
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[11, 2, 2], // Latency = 7, Repeat rate = 1
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[CR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPDivD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<31, [FPU_0]>],
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[39, 2, 2], // Latency = 35, Repeat rate = 31
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[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPDivS , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<16, [FPU_0]>],
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[24, 2, 2], // Latency = 20, Repeat rate = 16
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[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPFused , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [FPU_0]>],
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[11, 2, 2, 2], // Latency = 7, Repeat rate = 1
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[FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPRes , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<2, [FPU_0]>],
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[12, 2], // Latency = 8, Repeat rate = 2
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[FPR_Bypass, FPR_Bypass]>
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]>;
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// ===---------------------------------------------------------------------===//
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// e5500 machine model for scheduling and other instruction cost heuristics.
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def PPCE5500Model : SchedMachineModel {
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let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
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let LoadLatency = 6; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let Itineraries = PPCE5500Itineraries;
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}
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