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https://github.com/c64scene-ar/llvm-6502.git
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05ce489871
were overspecified when inheriting sub-subregisters, for instance: R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit. This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105063 91177308-0d34-0410-b5e6-96231b3b80d8
218 lines
6.9 KiB
C++
218 lines
6.9 KiB
C++
//===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly writer ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to the SystemZ assembly language.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "SystemZ.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZTargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Module.h"
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#include "llvm/Assembly/Writer.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Target/Mangler.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class SystemZAsmPrinter : public AsmPrinter {
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public:
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SystemZAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer) {}
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virtual const char *getPassName() const {
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return "SystemZ Assembly Printer";
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}
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void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
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const char* Modifier = 0);
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void printPCRelImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
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void printRIAddrOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
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const char* Modifier = 0);
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void printRRIAddrOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
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const char* Modifier = 0);
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void printS16ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) {
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O << (int16_t)MI->getOperand(OpNum).getImm();
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}
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void printS32ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) {
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O << (int32_t)MI->getOperand(OpNum).getImm();
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}
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void printInstruction(const MachineInstr *MI, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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void EmitInstruction(const MachineInstr *MI);
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};
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} // end of anonymous namespace
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#include "SystemZGenAsmWriter.inc"
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void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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printInstruction(MI, OS);
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OutStreamer.EmitRawText(OS.str());
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}
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void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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switch (MO.getType()) {
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case MachineOperand::MO_Immediate:
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O << MO.getImm();
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return;
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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return;
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case MachineOperand::MO_GlobalAddress: {
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const GlobalValue *GV = MO.getGlobal();
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O << *Mang->getSymbol(GV);
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// Assemble calls via PLT for externally visible symbols if PIC.
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if (TM.getRelocationModel() == Reloc::PIC_ &&
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!GV->hasHiddenVisibility() && !GV->hasProtectedVisibility() &&
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!GV->hasLocalLinkage())
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O << "@PLT";
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printOffset(MO.getOffset(), O);
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return;
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}
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case MachineOperand::MO_ExternalSymbol: {
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std::string Name(MAI->getGlobalPrefix());
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Name += MO.getSymbolName();
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O << Name;
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if (TM.getRelocationModel() == Reloc::PIC_)
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O << "@PLT";
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return;
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}
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default:
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assert(0 && "Not implemented yet!");
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}
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}
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void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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raw_ostream &O, const char *Modifier) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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switch (MO.getType()) {
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case MachineOperand::MO_Register: {
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assert (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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"Virtual registers should be already mapped!");
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unsigned Reg = MO.getReg();
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if (Modifier && strncmp(Modifier, "subreg", 6) == 0) {
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if (strncmp(Modifier + 7, "even", 4) == 0)
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Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::subreg_32bit);
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else if (strncmp(Modifier + 7, "odd", 3) == 0)
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Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::subreg_odd32);
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else
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assert(0 && "Invalid subreg modifier");
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}
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O << '%' << getRegisterName(Reg);
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return;
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}
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case MachineOperand::MO_Immediate:
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O << MO.getImm();
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return;
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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return;
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case MachineOperand::MO_JumpTableIndex:
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O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_'
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<< MO.getIndex();
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return;
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case MachineOperand::MO_ConstantPoolIndex:
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O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_'
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<< MO.getIndex();
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printOffset(MO.getOffset(), O);
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break;
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case MachineOperand::MO_GlobalAddress:
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O << *Mang->getSymbol(MO.getGlobal());
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break;
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case MachineOperand::MO_ExternalSymbol: {
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O << *GetExternalSymbolSymbol(MO.getSymbolName());
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break;
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}
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default:
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assert(0 && "Not implemented yet!");
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}
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switch (MO.getTargetFlags()) {
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default: assert(0 && "Unknown target flag on GV operand");
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case SystemZII::MO_NO_FLAG:
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break;
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case SystemZII::MO_GOTENT: O << "@GOTENT"; break;
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case SystemZII::MO_PLT: O << "@PLT"; break;
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}
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printOffset(MO.getOffset(), O);
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}
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void SystemZAsmPrinter::printRIAddrOperand(const MachineInstr *MI, int OpNum,
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raw_ostream &O,
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const char *Modifier) {
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const MachineOperand &Base = MI->getOperand(OpNum);
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// Print displacement operand.
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printOperand(MI, OpNum+1, O);
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// Print base operand (if any)
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if (Base.getReg()) {
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O << '(';
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printOperand(MI, OpNum, O);
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O << ')';
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}
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}
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void SystemZAsmPrinter::printRRIAddrOperand(const MachineInstr *MI, int OpNum,
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raw_ostream &O,
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const char *Modifier) {
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const MachineOperand &Base = MI->getOperand(OpNum);
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const MachineOperand &Index = MI->getOperand(OpNum+2);
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// Print displacement operand.
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printOperand(MI, OpNum+1, O);
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// Print base operand (if any)
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if (Base.getReg()) {
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O << '(';
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printOperand(MI, OpNum, O);
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if (Index.getReg()) {
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O << ',';
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printOperand(MI, OpNum+2, O);
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}
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O << ')';
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} else
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assert(!Index.getReg() && "Should allocate base register first!");
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}
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// Force static initialization.
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extern "C" void LLVMInitializeSystemZAsmPrinter() {
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RegisterAsmPrinter<SystemZAsmPrinter> X(TheSystemZTarget);
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}
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