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information and update all callers. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
396 lines
15 KiB
C++
396 lines
15 KiB
C++
//===-- AArch64AdvSIMDScalar.cpp - Replace dead defs w/ zero reg --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// When profitable, replace GPR targeting i64 instructions with their
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// AdvSIMD scalar equivalents. Generally speaking, "profitable" is defined
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// as minimizing the number of cross-class register copies.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TODO: Graph based predicate heuristics.
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// Walking the instruction list linearly will get many, perhaps most, of
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// the cases, but to do a truly thorough job of this, we need a more
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// wholistic approach.
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//
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// This optimization is very similar in spirit to the register allocator's
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// spill placement, only here we're determining where to place cross-class
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// register copies rather than spills. As such, a similar approach is
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// called for.
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//
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// We want to build up a set of graphs of all instructions which are candidates
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// for transformation along with instructions which generate their inputs and
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// consume their outputs. For each edge in the graph, we assign a weight
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// based on whether there is a copy required there (weight zero if not) and
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// the block frequency of the block containing the defining or using
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// instruction, whichever is less. Our optimization is then a graph problem
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// to minimize the total weight of all the graphs, then transform instructions
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// and add or remove copy instructions as called for to implement the
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// solution.
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64RegisterInfo.h"
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#include "AArch64Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-simd-scalar"
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// Allow forcing all i64 operations with equivalent SIMD instructions to use
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// them. For stress-testing the transformation function.
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static cl::opt<bool>
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TransformAll("aarch64-simd-scalar-force-all",
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cl::desc("Force use of AdvSIMD scalar instructions everywhere"),
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cl::init(false), cl::Hidden);
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STATISTIC(NumScalarInsnsUsed, "Number of scalar instructions used");
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STATISTIC(NumCopiesDeleted, "Number of cross-class copies deleted");
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STATISTIC(NumCopiesInserted, "Number of cross-class copies inserted");
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namespace {
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class AArch64AdvSIMDScalar : public MachineFunctionPass {
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MachineRegisterInfo *MRI;
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const AArch64InstrInfo *TII;
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private:
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// isProfitableToTransform - Predicate function to determine whether an
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// instruction should be transformed to its equivalent AdvSIMD scalar
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// instruction. "add Xd, Xn, Xm" ==> "add Dd, Da, Db", for example.
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bool isProfitableToTransform(const MachineInstr *MI) const;
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// transformInstruction - Perform the transformation of an instruction
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// to its equivalant AdvSIMD scalar instruction. Update inputs and outputs
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// to be the correct register class, minimizing cross-class copies.
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void transformInstruction(MachineInstr *MI);
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// processMachineBasicBlock - Main optimzation loop.
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bool processMachineBasicBlock(MachineBasicBlock *MBB);
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public:
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static char ID; // Pass identification, replacement for typeid.
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explicit AArch64AdvSIMDScalar() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &F) override;
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const char *getPassName() const override {
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return "AdvSIMD Scalar Operation Optimization";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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char AArch64AdvSIMDScalar::ID = 0;
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} // end anonymous namespace
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static bool isGPR64(unsigned Reg, unsigned SubReg,
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const MachineRegisterInfo *MRI) {
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if (SubReg)
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return false;
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
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return AArch64::GPR64RegClass.contains(Reg);
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}
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static bool isFPR64(unsigned Reg, unsigned SubReg,
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const MachineRegisterInfo *MRI) {
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
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SubReg == 0) ||
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(MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
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SubReg == AArch64::dsub);
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// Physical register references just check the register class directly.
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return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
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(AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
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}
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// getSrcFromCopy - Get the original source register for a GPR64 <--> FPR64
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// copy instruction. Return zero_reg if the instruction is not a copy.
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static unsigned getSrcFromCopy(const MachineInstr *MI,
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const MachineRegisterInfo *MRI,
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unsigned &SubReg) {
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SubReg = 0;
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// The "FMOV Xd, Dn" instruction is the typical form.
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if (MI->getOpcode() == AArch64::FMOVDXr ||
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MI->getOpcode() == AArch64::FMOVXDr)
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return MI->getOperand(1).getReg();
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// A lane zero extract "UMOV.d Xd, Vn[0]" is equivalent. We shouldn't see
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// these at this stage, but it's easy to check for.
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if (MI->getOpcode() == AArch64::UMOVvi64 && MI->getOperand(2).getImm() == 0) {
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SubReg = AArch64::dsub;
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return MI->getOperand(1).getReg();
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}
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// Or just a plain COPY instruction. This can be directly to/from FPR64,
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// or it can be a dsub subreg reference to an FPR128.
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if (MI->getOpcode() == AArch64::COPY) {
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if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
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MRI) &&
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isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
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return MI->getOperand(1).getReg();
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if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
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MRI) &&
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isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
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MRI)) {
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SubReg = MI->getOperand(1).getSubReg();
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return MI->getOperand(1).getReg();
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}
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}
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// Otherwise, this is some other kind of instruction.
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return 0;
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}
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// getTransformOpcode - For any opcode for which there is an AdvSIMD equivalent
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// that we're considering transforming to, return that AdvSIMD opcode. For all
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// others, return the original opcode.
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static int getTransformOpcode(unsigned Opc) {
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switch (Opc) {
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default:
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break;
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// FIXME: Lots more possibilities.
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case AArch64::ADDXrr:
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return AArch64::ADDv1i64;
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case AArch64::SUBXrr:
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return AArch64::SUBv1i64;
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case AArch64::ANDXrr:
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return AArch64::ANDv8i8;
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case AArch64::EORXrr:
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return AArch64::EORv8i8;
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case AArch64::ORRXrr:
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return AArch64::ORRv8i8;
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}
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// No AdvSIMD equivalent, so just return the original opcode.
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return Opc;
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}
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static bool isTransformable(const MachineInstr *MI) {
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int Opc = MI->getOpcode();
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return Opc != getTransformOpcode(Opc);
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}
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// isProfitableToTransform - Predicate function to determine whether an
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// instruction should be transformed to its equivalent AdvSIMD scalar
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// instruction. "add Xd, Xn, Xm" ==> "add Dd, Da, Db", for example.
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bool
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AArch64AdvSIMDScalar::isProfitableToTransform(const MachineInstr *MI) const {
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// If this instruction isn't eligible to be transformed (no SIMD equivalent),
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// early exit since that's the common case.
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if (!isTransformable(MI))
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return false;
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// Count the number of copies we'll need to add and approximate the number
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// of copies that a transform will enable us to remove.
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unsigned NumNewCopies = 3;
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unsigned NumRemovableCopies = 0;
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unsigned OrigSrc0 = MI->getOperand(1).getReg();
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unsigned OrigSrc1 = MI->getOperand(2).getReg();
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unsigned Src0 = 0, SubReg0;
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unsigned Src1 = 0, SubReg1;
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if (!MRI->def_empty(OrigSrc0)) {
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MachineRegisterInfo::def_instr_iterator Def =
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MRI->def_instr_begin(OrigSrc0);
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assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
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Src0 = getSrcFromCopy(&*Def, MRI, SubReg0);
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// If the source was from a copy, we don't need to insert a new copy.
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if (Src0)
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--NumNewCopies;
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// If there are no other users of the original source, we can delete
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// that instruction.
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if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0))
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++NumRemovableCopies;
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}
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if (!MRI->def_empty(OrigSrc1)) {
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MachineRegisterInfo::def_instr_iterator Def =
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MRI->def_instr_begin(OrigSrc1);
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assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
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Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
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if (Src1)
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--NumNewCopies;
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// If there are no other users of the original source, we can delete
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// that instruction.
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if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1))
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++NumRemovableCopies;
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}
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// If any of the uses of the original instructions is a cross class copy,
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// that's a copy that will be removable if we transform. Likewise, if
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// any of the uses is a transformable instruction, it's likely the tranforms
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// will chain, enabling us to save a copy there, too. This is an aggressive
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// heuristic that approximates the graph based cost analysis described above.
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unsigned Dst = MI->getOperand(0).getReg();
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bool AllUsesAreCopies = true;
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for (MachineRegisterInfo::use_instr_nodbg_iterator
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Use = MRI->use_instr_nodbg_begin(Dst),
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E = MRI->use_instr_nodbg_end();
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Use != E; ++Use) {
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unsigned SubReg;
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if (getSrcFromCopy(&*Use, MRI, SubReg) || isTransformable(&*Use))
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++NumRemovableCopies;
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// If the use is an INSERT_SUBREG, that's still something that can
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// directly use the FPR64, so we don't invalidate AllUsesAreCopies. It's
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// preferable to have it use the FPR64 in most cases, as if the source
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// vector is an IMPLICIT_DEF, the INSERT_SUBREG just goes away entirely.
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// Ditto for a lane insert.
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else if (Use->getOpcode() == AArch64::INSERT_SUBREG ||
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Use->getOpcode() == AArch64::INSvi64gpr)
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;
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else
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AllUsesAreCopies = false;
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}
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// If all of the uses of the original destination register are copies to
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// FPR64, then we won't end up having a new copy back to GPR64 either.
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if (AllUsesAreCopies)
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--NumNewCopies;
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// If a transform will not increase the number of cross-class copies required,
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// return true.
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if (NumNewCopies <= NumRemovableCopies)
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return true;
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// Finally, even if we otherwise wouldn't transform, check if we're forcing
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// transformation of everything.
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return TransformAll;
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}
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static MachineInstr *insertCopy(const AArch64InstrInfo *TII, MachineInstr *MI,
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unsigned Dst, unsigned Src, bool IsKill) {
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MachineInstrBuilder MIB =
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BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AArch64::COPY),
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Dst)
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.addReg(Src, getKillRegState(IsKill));
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DEBUG(dbgs() << " adding copy: " << *MIB);
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++NumCopiesInserted;
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return MIB;
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}
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// transformInstruction - Perform the transformation of an instruction
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// to its equivalant AdvSIMD scalar instruction. Update inputs and outputs
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// to be the correct register class, minimizing cross-class copies.
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void AArch64AdvSIMDScalar::transformInstruction(MachineInstr *MI) {
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DEBUG(dbgs() << "Scalar transform: " << *MI);
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MachineBasicBlock *MBB = MI->getParent();
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int OldOpc = MI->getOpcode();
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int NewOpc = getTransformOpcode(OldOpc);
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assert(OldOpc != NewOpc && "transform an instruction to itself?!");
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// Check if we need a copy for the source registers.
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unsigned OrigSrc0 = MI->getOperand(1).getReg();
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unsigned OrigSrc1 = MI->getOperand(2).getReg();
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unsigned Src0 = 0, SubReg0;
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unsigned Src1 = 0, SubReg1;
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if (!MRI->def_empty(OrigSrc0)) {
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MachineRegisterInfo::def_instr_iterator Def =
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MRI->def_instr_begin(OrigSrc0);
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assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
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Src0 = getSrcFromCopy(&*Def, MRI, SubReg0);
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// If there are no other users of the original source, we can delete
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// that instruction.
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if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0)) {
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assert(Src0 && "Can't delete copy w/o a valid original source!");
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Def->eraseFromParent();
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++NumCopiesDeleted;
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}
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}
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if (!MRI->def_empty(OrigSrc1)) {
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MachineRegisterInfo::def_instr_iterator Def =
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MRI->def_instr_begin(OrigSrc1);
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assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
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Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
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// If there are no other users of the original source, we can delete
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// that instruction.
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if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1)) {
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assert(Src1 && "Can't delete copy w/o a valid original source!");
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Def->eraseFromParent();
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++NumCopiesDeleted;
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}
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}
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// If we weren't able to reference the original source directly, create a
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// copy.
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if (!Src0) {
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SubReg0 = 0;
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Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
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insertCopy(TII, MI, Src0, OrigSrc0, true);
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}
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if (!Src1) {
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SubReg1 = 0;
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Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
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insertCopy(TII, MI, Src1, OrigSrc1, true);
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}
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// Create a vreg for the destination.
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// FIXME: No need to do this if the ultimate user expects an FPR64.
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// Check for that and avoid the copy if possible.
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unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
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// For now, all of the new instructions have the same simple three-register
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// form, so no need to special case based on what instruction we're
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// building.
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BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst)
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.addReg(Src0, getKillRegState(true), SubReg0)
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.addReg(Src1, getKillRegState(true), SubReg1);
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// Now copy the result back out to a GPR.
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// FIXME: Try to avoid this if all uses could actually just use the FPR64
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// directly.
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insertCopy(TII, MI, MI->getOperand(0).getReg(), Dst, true);
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// Erase the old instruction.
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MI->eraseFromParent();
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++NumScalarInsnsUsed;
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}
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// processMachineBasicBlock - Main optimzation loop.
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bool AArch64AdvSIMDScalar::processMachineBasicBlock(MachineBasicBlock *MBB) {
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bool Changed = false;
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;) {
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MachineInstr *MI = I;
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++I;
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if (isProfitableToTransform(MI)) {
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transformInstruction(MI);
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Changed = true;
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}
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}
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return Changed;
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}
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// runOnMachineFunction - Pass entry point from PassManager.
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bool AArch64AdvSIMDScalar::runOnMachineFunction(MachineFunction &mf) {
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bool Changed = false;
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DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n");
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const TargetMachine &TM = mf.getTarget();
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MRI = &mf.getRegInfo();
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TII = static_cast<const AArch64InstrInfo *>(
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TM.getSubtargetImpl()->getInstrInfo());
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// Just check things on a one-block-at-a-time basis.
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for (MachineFunction::iterator I = mf.begin(), E = mf.end(); I != E; ++I)
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if (processMachineBasicBlock(I))
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Changed = true;
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return Changed;
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}
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// createAArch64AdvSIMDScalar - Factory function used by AArch64TargetMachine
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// to add the pass to the PassManager.
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FunctionPass *llvm::createAArch64AdvSIMDScalar() {
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return new AArch64AdvSIMDScalar();
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}
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